Alleviation of Negative-Bias Temperature Instability in Si p-FinFETs With ALD W Gate-Filling Metal by Annealing Process Optimization

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate stack, fresh interface quality, threshold voltage shift (
${\Delta }$

V
$_{T}$
), pre-existing traps (
${\Delta } {N} _{\mathrm {HT}}$
), generated traps, and their relative contributions were studied. The time exponents of
${\Delta }$

V
$_{T}$
, the impacts of stress bias and temperature on NBTI degradation, and the recovery kinetics of the generated traps were analyzed. For devices with a B
₂
H
₆
-based W-filling metal, a 34% reduction in the fresh interface states, reduced
${\Delta }$

V
$_{T}$
, and a 29% improvement in the operation overdrive voltage could be achieved by optimizing the annealing conditions. The NBTI is alleviated mainly because of the reduction in the generated traps, while the energy distribution of
${\Delta } {N} _{\mathrm {HT}}$
is insensitive to the annealing conditions. Furthermore, the relative contribution of the generated bulk insulator traps to the total number of generated traps could be reduced by optimizing the annealing conditions.