IEEE Journal of the Electron Devices Society

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughnes... View full abstract»

The pinned photodiode is the primary photodetector structure used in most CCD and CMOS image sensors. This paper reviews the development, physics, and technology of the pinned photodiode. View full abstract»

Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the qua... View full abstract»

The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage (VDD). In this paper, using atomistic quantum models that are in agreement with experimental TFET devices, we are reviewing TFETs prospects at LG= 13 nm node together with the main challenges and be... View full abstract»

Progress in the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology. Experiments lag the projections, but sub-threshold swings less than 60 mV/decade are now reported in 14 TFETs. The lowest measured sub-threshold swings approaches 20 mV/decade, however, the measurements at these lowes... View full abstract»

A red-light micro LED display made of an AlGaInP epilayer with a resolution of$64 \times 32$pixels, a pitch of$175~ \mu {\mathrm {m}}$and a luminous area of$1 ~{\mathrm {cm}} \times 0.5~ {\mathrm {cm}}$ View full abstract»

Cross point RRAM arrays is the emerging area for future memory devices due to their high density, excellent scalability. Sneak path problem is the main disadvantage of cross point structures which needed to be overcome to produce real devices. Various self-rectifying cells like complementary resistive cell, hybrid RRAM cell, valence modulated conductive oxide RRAM and non-linear resistive memory w... View full abstract»

The corresponding energy landscape and surface potential are deduced from the experimental ferroelectricity of HfZrO2(HZO) for low-power steep-slope transistor applications. The anti-ferroelectric (AFE) in annealed 600°C HZO extracted electrostatic potential gain from the measured polarization hysteresis loop and calculated subthreshold swing 33 mV/dec over six decades of IDS... View full abstract»

This paper demonstrates a pixel circuit of seven thin film transistors (TFTs) and two capacitors that drives an AC driven OLED (AC-OLED) at a simultaneous emission scheme. Because the AC-OLED is composed of two OLED units connected in opposite directions, the proposed circuit drives the current programmed once during a frame time in both ways. Since one OLED unit emits the light for about half fra... View full abstract»

Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with consid... View full abstract»

In this paper, a novel normally off p-gallium nitride (GaN) gate high electron-mobility transistor (HEMT) with composite AlN/Al0.17Ga0.83N/Al0.3Ga0.7N barrier layers is proposed. Compared to the standard (STD) p-GaN/AlGaN/GaN HEMT structure, the composite barriers (CB) with AlN etchstop layer can effectively improve the uniformity of the device threshold... View full abstract»

In this paper, we report the design and fabrication of fine-pitch and pixelated-addressed micro-light emitting diode (LED) arrays with emission wavelengths of red (R), green (G), blue (B), and infrared (IR). The arrays have a resolution of 8×8 with monochromatic LED chips directly bonded to custom-designed printed circuit boards to form pixelated matrix. R, G, B, and IR micro-LED arrays with a pix... View full abstract»

The fabrication of AlGaInP-based flip-chip micro light-emitting-diodes (LED; emitting area: 4.5 mil × 5 mil) with horizontal electrodes is reported in this paper. The thickness of the epitaxial layer of the thin LED structure was reduced to 50% of that of the traditional thick LED, whereas carrier concentration in the n-type GaAs contact layer was increased to 5×1018cm-3to me... View full abstract»

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-$\mu \text{m}$and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperature... View full abstract»

Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devices. To solve this problem, we developed a low temperature III-V and Ge layer stacking process using ... View full abstract»

The negative capacitance (NC) of ferroelectric materials has paved the way for achieving sub-60-mV/decade switching feature in complementary metal-oxide-semiconductor (CMOS) field-effect transistors, by simply inserting a ferroelectric thin layer in the gate stack. However, in order to utilize the ferroelectric capacitor (as a breakthrough technique to overcome the Boltzmann limit of the device us... View full abstract»

This paper presents the experimental characterization of different rectifier circuits using indium–gallium–zinc-oxide thin-film transistor technologies either at NFC or a high frequency range (13.56 MHz) of RFID. These circuits include a single ended rectifier, its differential counterpart, a bridge rectifier, and a cross-coupled full wave rectifier. Diodes were implemented with transistors using ... View full abstract»

In this paper, the impacts of work function variation (WFV), line-edge roughness (LER), and ferroelectric properties variation on the threshold voltage, subthreshold swing (SS), Ion, and Ioff variations are analyzed comprehensively for negative capacitance ultra-thin body SOI MOSFETs (NCSOI) compared with SOI MOSFETs (SOI). For LER induced threshold voltage variation ( View full abstract»

Ferroelectric field effect transistors (FeFETs) based on lead zirconate titanate (PZT) ferroelectric material and amorphous-indium-gallium-zinc oxide (a-IGZO) were developed and characterized. The PZT material was processed by a sol-gel method and then used as ferroelectric gate. The a-IGZO thin films, having the role of channel semiconductor, were deposited by radio-frequency magnetron sputtering... View full abstract»

A ferroelectric thin film transistor (Fe-TFT) based on annealing-free hafnium zirconium oxide (HfZrO) is demonstrated in this paper. Indium zinc oxide was used as channel semiconductor. The as-deposited 30-nm HfZrO film implemented as gate dielectric was proved to be crystallized with a mixture of monoclinic, tetragonal, and orthorhombic phases and showed ferroelectricity naturally. Thus, high tem... View full abstract»

We report a capacitive touch sensor using a-IGZO TFTs as active components to improve touch sensitivity and output robustness. The output potential difference between touched/untouched states is 1.7 V without readout buffer. Additionally, due to the fully compatible gate driving clocks with conventional active-matrix backplane, the integration of the capacitive touch sensor with AMOLED display wit... View full abstract»

We experimentally demonstrate that hysteresis of negative capacitance (NC) Ge pFETs is reduced through modulating the ferroelectric properties in HfZrOx(HZO) by changing the post annealing temperature. As annealing temperature varies from 350 °C to 450 °C, HZO exhibits a significant increasing in the ratio of remnant polarization Prto coercive field Ec, which resul... View full abstract»

Flexible radio-frequency (RF) electronics require materials which possess both exceptional electronic properties and high-strain limits. While flexible graphene field-effect transistors (GFETs) have demonstrated significantly higher strain limits than FETs fabricated from thin films of Si and III-V semiconductors, to date RF performance has been comparatively worse, limited to the low GHz frequenc... View full abstract»

This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300, 77, and 4.2 K from dc measurements made on various geometries. The simplified-EKV compact model is used to accurately capture the dc characteris... View full abstract»

This comprehensive study of the horizontally p-type stacked nanosheets inversion mode thinfilm transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS-TFT) structures. The stacked nanosheets device structure, fabrication, and electrical characteristics are analyzed. The SNS-GAATFT reveals better performance to multi-gate SNS-TFT. The proposed inversion mode SNS-TFT has properties of the e... View full abstract»