Modeling and Controlling Layout Dependent Variations in Semi-Additive Copper Electrochemical Plating

An empirical model is proposed for predicting layout dependent thickness variations in the semi-additive copper electrochemical plating (ECP) process. These variations are believed to be caused by the uneven depletion of copper sulfate during plating, causing low pattern density areas to plate faster than higher pattern density areas. Effective pattern density is extracted from the layout using a spatial filter and then mapped to the growth rates using a non-linear function. Test structures are designed that represent a wide range of feature sizes and pattern densities. After plating, these structures are profiled and used to fit the model, while other structures are used to validate its accuracy. Comparisons between the validation predictions and the experimental results show an average balanced root mean squared error (BRMSE) of 0.292 μm, and a corresponding R² value of 0.90. Fill patterns are then proposed and shown to control plating variations, by controlling pattern density. Finally, across-chip growth rate variations for a realistic interconnect layer are predicted, and experimentally confirmed.

I. Introduction

Advanced packaging technologies including 2.5D integration are attractive due to the low fabrication costs and desirable electrical, thermal and mechanical characteristics [1]–[3]. These systems utilize redistribution layers (RDLs), separate packaging layers that use copper interconnects to connect multiple die to one another, as well as to external I/O ports.