Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links

This paper presents a source-synchronous receiver architecture for use in parallel optical links. The proposed system is reconfigurable, allowing any channel to be used as a clock or data lane. The architecture is designed for mode-division multiplexed (MDM) optical links with forwarded clocks and allows the sensitive clock signal to be placed in the lane with the least amount of optical crosstalk for a given photonic interconnect. This configurability, which accounts for variation in integrated optics by leveraging the more robust electronic chip, optimizes the performance in electronic/optic codesigned solutions and may improve the yield. The architecture contains a dynamic clock distribution network, able to send a reference clock signal from the chosen clock receiver to any other data-configured receiver. The proposed architecture has been implemented on an experimental chip consisting of two receivers designed in the 65-nm CMOS technology. Electrical measurements at 8 Gb/s were done, and bit error rate curves are presented. They demonstrate the ability to swap and repurpose the clock and data inputs between the receivers, with similar sensitivity upon reconfiguration as a proof of concept.