Well-Posed Verilog-A Compact Model for Phase Change Memory

In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge₂ Sb₂ Te₅, (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.

I. Introduction

Phase change memory (PCM) is a non-volatile memory technology that is emerging as a leading contender for storage class memories as well as in-memory computing applications based on crossbar array architectures with co-located memory and processing units [1]–[3]. Emerging memory devices such as PCM, STT-RAMs (Spin-Transfer Torque Random Access Memory) and RRAM (Resistive RAM) have also shown the capability to be programmed to store analog resistance levels, and are being explored for realizing area and power efficient accelerators for machine learning and embedded AI applications [4]–[8].