Machine intelligence through 3D waferscale integration

Bringing computing systems to the stage of Machine Intelligence will require a massive scaling in processing, memory, and interconnectivity, and thus a major change in how electronic systems are designed. Long overlooked because of its unsuitability for the exacting demands of enterprise computing, 3D waferscale integration offers a promising scaling path, due in large part to the fault-tolerant nature of many cognitive algorithms. This work explores this scaling path in greater detail, invoking a simple model of brain connectivity to examine the potential for 3D waferscale integration to meet the demanding interconnectivity requirements of Machine Intelligence.

I. Introduction

Computing systems have made tremendous strides in the area of cognitive computing, evolving from transactional processing to tasks requiring fuzzier analysis such as classification, pattern recognition, and anomaly detection [1]. At the algorithm level, these advances fall under the broad category of Machine Learning, characterized by solving a specific task by defining and optimizing an objective function. In Deep Learning, a particular area of Machine Learning, a large network having fixed connectivity is trained to a specific task using large amounts of labeled data.