I. Introduction
The new generation of phase-locked loops (PLLs) on mixed-mode ICs is either partly digital [1] or all-digital [2]–[10], uses a time-to-digital converter (TDC) instead of a linear phase detector, and a digital filter in place of an the R-C filter network. The underlying concept dates back to compact spaceborne communications systems in the early 1970s; see, for instance, [11]. In this paper we examine partly or fully digital PLLs that use a bang-bang phase detector, a one-bit time-to-digital converter often realized by a regenerative clocked comparator as shown in Fig. 1 [1], [3], [7], [10], [12]. It is similar to a one-bit delta-sigma A/D converter, which is preferred over a multibit converter when the conversion bandwidth allows. This is because a one-bit, two-level quantizer is perfectly “linear” in the sense that a straight line always passes through two points, whereas a multilevel quantizer can never be perfectly so because of practical sources of non-uniformity among more than two threshold levels.
Phase-locked loop employing a binary bang-bang phase detector.