26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltage

Clock network optimization is substantially affected by the operating voltage V_DD, as the clock skew is dominated by different mechanisms and has a different balance between wire and repeater delay at different V_DD (Fig. 26.3.1). At above-threshold V_DD, deep clock networks with several levels of repeaters are needed to control the clock slope in wires [1]. At sub-threshold V_DD, shallow networks are needed as the gate delay dominates, and the random clock skew approximately grows proportionally to the square root of the number of levels [2]. At such V_DD, the skew of clock networks designed at above-threshold V_DD is much larger than at the nominal voltage V_DD,nom, thus assuring a reasonable skew budget across a wide range of V_DD is challenging [1-3]. To date, clock skew at low V_DD has been mitigated via moderately deep networks with long-channel LVT buffers [1], design methodologies [2], [4], and voltage-adaptive delay insertion across different clock domains [3]. However, no voltage adaption has been performed within a clock domain.