Abstract:
Clock network optimization is substantially affected by the operating voltage VDD, as the clock skew is dominated by different mechanisms and has a different balance betw...Show MoreMetadata
Abstract:
Clock network optimization is substantially affected by the operating voltage VDD, as the clock skew is dominated by different mechanisms and has a different balance between wire and repeater delay at different VDD (Fig. 26.3.1). At above-threshold VDD, deep clock networks with several levels of repeaters are needed to control the clock slope in wires [1]. At sub-threshold VDD, shallow networks are needed as the gate delay dominates, and the random clock skew approximately grows proportionally to the square root of the number of levels [2]. At such VDD, the skew of clock networks designed at above-threshold VDD is much larger than at the nominal voltage VDD,nom, thus assuring a reasonable skew budget across a wide range of VDD is challenging [1-3]. To date, clock skew at low VDD has been mitigated via moderately deep networks with long-channel LVT buffers [1], design methodologies [2], [4], and voltage-adaptive delay insertion across different clock domains [3]. However, no voltage adaption has been performed within a clock domain.
Date of Conference: 05-09 February 2017
Date Added to IEEE Xplore: 06 March 2017
ISBN Information:
Electronic ISSN: 2376-8606