A power efficient MDAC design with correlated double sampling for a 2-step-flash ADC

This paper describes implementation issues for high speed 2-step-flash analog-to-digital converters (ADCs) without digital correction. A novel implementation for a multiplying digital-to-analog converter (MDAC) is described, which is a sample-and-hold amplifier, which includes a DAC, residue amplification and correlated double sampling (CDS), thereby omitting two-phase compensation differences. No digital correction is needed because linearity of the 2-step-flash ADC is provided by a capacitor-array matching and CDS prevents missing codes due to offset in the MDAC.