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NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation | IEEE Journals & Magazine | IEEE Xplore

NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation


Abstract:

The implicit-connection-graph-based router is superior to the tile-based router in terms of routing graph construction and point querying. However, the implicit connectio...Show More

Abstract:

The implicit-connection-graph-based router is superior to the tile-based router in terms of routing graph construction and point querying. However, the implicit connection graph has a higher degree of routing graph complexity. In this paper, a new multilayer implicit-connection-graph-based gridless router called NEMO is developed. Unlike the first implicit-connection-graph-based router that embeds all routing layers onto a routing plane, NEMO constructs a routing plane for each routing layer. Additionally, each routing plane comprises tiles, not an array of grid points with their connecting edges, and consequently, the complexity of the routing problem decreases. Each grid point then represents exactly one tile or its left-bottom corner such that a tile query is equivalent to any point query inside the queried tile, and a grid maze becomes tile propagation. Furthermore, to accelerate path search, continuous space tiles are combined as a pseudo maximum horizontally or vertically stripped tile. Experimental results reveal that NEMO conducts a point-to-point path search around ten times faster than the implicit-connection-graph-based router. General-purpose routing by NEMO also improves routing performance by approximately 1.69times-55.82 times, as compared to previously published works based on a set of commonly used MCNC benchmark circuits
Page(s): 705 - 718
Date of Publication: 19 March 2007

ISSN Information:


I. Introduction

In the era of deep-submicrometer (DSM) technology and system-on-chip design methodology, very large-scale integrated (VLSI) designs engender challenges in optimizing layouts resulting from ongoing reductions in device size, wire width, and wire space. Interconnection optimization is crucial in minimizing delay and noise and optimizing reliability of modern chip designs. Wire sizing and wire spacing have been proposed as techniques in optimizing interconnectivity, thus imposing variable-width and variable-space constraints on detailed routers. Variable-rule routing raises the requirement for a router other than a uniform-grid router. Nonuniform-grid routers and tile-based routers, which are also called gridless routers, are commonly employed in variable-rule routing [1]–[12]. To accommodate variable-rule routing, gridless routers require more complex data structures than do uniform-grid routers to construct routing graphs quickly, as well as to verify the design rule check legality of a move on a routing graph. In the meantime, modern designs have substantially increased the instance size of the routing problem to motivate novel routing techniques and frameworks for high-performance gridless routing. Among these designs, multilevel design framework [13]–[18] and routing graph reduction [20] have been extensively investigated and have been successfully adopted to improve the routing performance.

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