I. Introduction
In the era of deep-submicrometer (DSM) technology and system-on-chip design methodology, very large-scale integrated (VLSI) designs engender challenges in optimizing layouts resulting from ongoing reductions in device size, wire width, and wire space. Interconnection optimization is crucial in minimizing delay and noise and optimizing reliability of modern chip designs. Wire sizing and wire spacing have been proposed as techniques in optimizing interconnectivity, thus imposing variable-width and variable-space constraints on detailed routers. Variable-rule routing raises the requirement for a router other than a uniform-grid router. Nonuniform-grid routers and tile-based routers, which are also called gridless routers, are commonly employed in variable-rule routing [1]–[12]. To accommodate variable-rule routing, gridless routers require more complex data structures than do uniform-grid routers to construct routing graphs quickly, as well as to verify the design rule check legality of a move on a routing graph. In the meantime, modern designs have substantially increased the instance size of the routing problem to motivate novel routing techniques and frameworks for high-performance gridless routing. Among these designs, multilevel design framework [13]–[18] and routing graph reduction [20] have been extensively investigated and have been successfully adopted to improve the routing performance.