A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS

To simultaneously advance phase noise (PN) performance at a wide frequency-tuning range (FTR) while using the standard supply levels, this letter proposes a multistory multicore multimode oscillator topology based on the following ideas: 1) the N number of cores reduces the PN by $10 \log (N)$ dB, and the circular geometry of inductors promotes their high-quality $(Q)$ -factors and compact layout; 2) the multiple stacked cores exploiting current reuse improve the figure of merit (FoM) using an nMOS-only oscillator configuration under a standard supply; and 3) the multiple modes expand the FTR by leveraging the interstory coupling with all oscillator cores turned on simultaneously, only occupying a single resonator’s footprint. A two-story quad-core dual-mode voltage-controlled oscillator (VCO) prototype is fabricated in 65-nm CMOS. Using a standard 1.2-V supply, it achieves PN of −111.3 to −106.2 dBc/Hz at 1-MHz offset over a 25.0–35.9-GHz FTR (35.8%), a 186.5–189.1-dBc/Hz FoM, and a 197.6–200.2-dBc/Hz $\rm {FoM}_{T}$ (i.e., FoM with normalized FTR).