A Two-Story Quad-Core Dual-Mode VCO in 65-nm CMOS

To simultaneously advance phase noise (PN) performance at a wide frequency-tuning range (FTR) while using the standard supply levels, this letter proposes a multi-story multi-core multi-mode oscillator topology based on the following ideas: 1) The N number of cores reduces the phase noise (PN) by 10log(N) dB, and the circular-geometry of inductors promotes their high quality (Q)-factors and compact layout. 2) The multiple stacked cores exploiting current reuse improve the figure-of-merit (FoM) using an NMOS-only oscillator configuration under a standard supply. 3) The multiple modes expand the FTR by leveraging the inter-story coupling with all oscillator cores turned on simultaneously, only occupying a single resonator’s footprint. A two-story quad-core dual-mode voltage-controlled oscillator (VCO) prototype is fabricated in 65-nm CMOS. Using a standard 1.2-V supply, it achieves PN of –111.3 –106.2 dBc/Hz at 1-MHz offset over a 25.0–35.9-GHz FTR (35.8%), a 186.5–189.1-dBc/Hz FoM, a 197.6–200.2-dBc/Hz FoMT (i.e., FoM with normalized FTR).