A Radiation-Hardened Double Node Upset Latch Design for Nanoscale CMOS Technologies

This paper presents a newly designed latch which provides resilience to double node upsets (DNU) caused by radiations like alpha or harmful rays. A latch is used in all the data storage devices which makes latch play a vital role in modern circuits. The basic principle of the proposed latch is on interlocked feedback hold technique. The circuit comprises three transmission gates, three Muller C elements (MCE) as well as three clocked Muller C elements (CMCE). The proposed latch has $29.79 \%$ less total power consumption, $42.04 \%$ less switching power consumption and $\mathbf{1 8. 0 9} \%$ less D to Q delay in comparison to the newer DNU latch design. The proposed latch also improves 42.5% energy delay product when compared with recently reported radiation hardened latches. The latch is designed in 90nm CMOS technology and the implementation, simulation and corner analysis of circuits are carried out in the Cadence Virtuoso EDA tool.