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Chaudhry Indra Kumar - IEEE Xplore Author Profile
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Chaudhry Indra Kumar

Also published under: Chaudhary Indra Kumar

Publications
16
Citations
91
Publications by Year
20112024
Co-Authors:
Show All Co-Authors (32)
Image of author Chaudhry Indra Kumar

Chaudhry Indra Kumar

Also published under: Chaudhary Indra Kumar

Affiliation

EE Department
Delhi Technological University
New Delhi, India

Publication Topics

Biography

Chaudhry Indra Kumar is currently working toward the Ph.D. degree at the Electronics and Communication Engineering Department, IIT Roorkee, Roorkee, India.,His current research interests include variation aware latch/flip-flop design and nearthreshold/subthreshold circuit design.(Based on document published on 8 May 2019).
Publications
16
Citations
91
Publications by Year
20112024
Co-Authors:
Show All Co-Authors (32)
Author's Published Works

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Modeling Novel Negative Resistance Hyper-FETs Using Neural Regressor Networks

Ritika Sorot;Sonam Rewari;Chaudhry Indra Kumar

2024 IEEE Silchar Subsection Conference (SILCON 2024)
Year: 2024 | Conference Paper |
This paper proposes the use of regressor networks for modeling evolving hybrid phase transition FETs as their device physics is still not clear. Hyper-FET is modeled using multi layer perceptron regressor and random regressor networks. Predictions made by random regressor based neural model are closer to the accurate values as out of bag error and mean square error is approximately 98 percent less...Show More

Modeling Novel Negative Resistance Hyper-FETs Using Neural Regressor Networks

Ritika Sorot;Sonam Rewari;Chaudhry Indra Kumar

Year: 2024 | Conference Paper |

VM Universal Biquad Filter Using Single VDCC

Devanshu Saxena;Garima Mann;Chaudhry Indra Kumar

2024 4th International Conference on Advancement in Electronics & Communication Engineering (AECE)
Year: 2024 | Conference Paper |
This paper presented a voltage mode (VM), multiple input and single output (MISO) universal biquad filter using only one voltage differencing current conveyor (VDCC) and three passive components. The proposed configuration is capable of realizing second-order low pass filter (LPF), high pass filter (HPF), band pass filter (BPF), band-reject filter (BRF) and all pass filter (APF). The proposed biqu...Show More

VM Universal Biquad Filter Using Single VDCC

Devanshu Saxena;Garima Mann;Chaudhry Indra Kumar

Year: 2024 | Conference Paper |

A Low Leakage Near-Threshold 11T SRAM Cell with enhanced Static Noise Margins

Rachit Bhatia;Chaudhry Indra Kumar;Anupama

2024 1st International Conference on Sustainable Computing and Integrated Communication in Changing Landscape of AI (ICSCAI)
Year: 2024 | Conference Paper |
Operating the SRAM cells at near-threshold voltages is an effective way to achieve higher energy efficiency, though it typically compromises stability and performance. This paper presents a distinctive 11T SRAM cell for near threshold operation, characterised by high stability (hold/read/write static noise margins) in addition to reduced leakage power. The core circuit comprises an asymmetric desi...Show More

A Low Leakage Near-Threshold 11T SRAM Cell with enhanced Static Noise Margins

Rachit Bhatia;Chaudhry Indra Kumar;Anupama

Year: 2024 | Conference Paper |

A Radiation-Hardened Double Node Upset Latch Design for Nanoscale CMOS Technologies

Promit Mandal;Prince Kumar;Saarthak Vijay Singh;Chaudhry Indra Kumar

2024 IEEE Workshop on Complexity in Engineering (COMPENG)
Year: 2024 | Conference Paper |
This paper presents a newly designed latch which provides resilience to double node upsets (DNU) caused by radiations like alpha or harmful rays. A latch is used in all the data storage devices which makes latch play a vital role in modern circuits. The basic principle of the proposed latch is on interlocked feedback hold technique. The circuit comprises three transmission gates, three Muller C el...Show More

A Radiation-Hardened Double Node Upset Latch Design for Nanoscale CMOS Technologies

Promit Mandal;Prince Kumar;Saarthak Vijay Singh;Chaudhry Indra Kumar

Year: 2024 | Conference Paper |

High Performance CMOS Voltage Level Shifters Design for Low Voltage Applications

Ananya Kapoor;Chaitanya Shanker Jha;Ayush Thapar;Chaudhry Indra Kumar

2023 International Conference for Advancement in Technology (ICONAT)
Year: 2023 | Conference Paper |
Cited by: Papers (3)
To convert signals from one logic level or voltage level to another, a level shifter circuit is used in analog and digital integrated circuits (IC’s). It is also known as a voltage level translator or a logic-level shifter. An integrated circuit voltage level changer allows for compatibility across integrated circuits with various voltage needs. In this work, a voltage level shifter that efficient...Show More

High Performance CMOS Voltage Level Shifters Design for Low Voltage Applications

Ananya Kapoor;Chaitanya Shanker Jha;Ayush Thapar;Chaudhry Indra Kumar

Year: 2023 | Conference Paper |

High Performance Energy Efficient CMOS Voltage Level Shifter Design

Ravi Nandan Ray;Madan Mohan Tripathi;Chaudhary Indra Kumar

2022 2nd International Conference on Intelligent Technologies (CONIT)
Year: 2022 | Conference Paper |
Cited by: Papers (2)
This paper presents an energy efficient voltage CMOS voltage level shifter. Voltage level shifter is used for multi-supply design applications. The main purpose of voltage level shifter is to convert the voltage level from one level to another. We verified our voltage level shifter in ASAP7 7nm Fin-Fet technology. The proposed voltage level shifter is based on differential cascade voltage switch l...Show More

High Performance Energy Efficient CMOS Voltage Level Shifter Design

Ravi Nandan Ray;Madan Mohan Tripathi;Chaudhary Indra Kumar

Year: 2022 | Conference Paper |

An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN

Dinesh Kushwaha;Ashish Joshi;Chaudhry Indra Kumar;Neha Gupta;Sandeep Miryala;Rajiv V. Joshi;Sudeb Dasgupta;Anand Bulusu

IEEE Transactions on Circuits and Systems II: Express Briefs
Year: 2022 | Volume: 69, Issue: 4 | Journal Article |
Cited by: Papers (10)
In this brief, we present an energy-efficient and high compute signal-to-noise ratio (CSNR) XNOR and accumulation (XAC) scheme for binary neural networks (BNNs). Transmission gates achieve a large compute signal margin (CSM) and high CSNR for accurate XAC operation. The 10T1C XNOR SRAM bit-cell performs the in-memory XAC operation without pre-charging the larger bitline capacitances and significan...Show More

An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN

Dinesh Kushwaha;Ashish Joshi;Chaudhry Indra Kumar;Neha Gupta;Sandeep Miryala;Rajiv V. Joshi;Sudeb Dasgupta;Anand Bulusu

Year: 2022 | Volume: 69, Issue: 4 | Journal Article |

A Single Node Upset Hardened Latch Design in NTV Regime

Chaudhry Indra Kumar

2021 IEEE 4th International Conference on Computing, Power and Communication Technologies (GUCON)
Year: 2021 | Conference Paper |
As CMOS technology scales down, state holding circuits are more prone to single node upset (SNU) due to the externally induced radiation phenomena. Therefore, the tolerance of the state holding circuits against SNU is strict requirement in nanoscale CMOS design. In this paper we present a unique high performance SNU hardened latch. The presented latch enhanced the soft error tolerance by using one...Show More

A Single Node Upset Hardened Latch Design in NTV Regime

Chaudhry Indra Kumar

Year: 2021 | Conference Paper |

Time-Borrowing Flip-Flop Architecture for Multi-Stage Timing Error Resilience in DVFS Processors

Avisekh Ghosh;Mohd Saif Naseem;Chaudhry Indra Kumar

2021 International Conference on Intelligent Technologies (CONIT)
Year: 2021 | Conference Paper |
Cited by: Papers (1)
Near-threshold voltage (NTV) design has been proposed for low-power VLSI designs across a wide range of applications due to its optimal Energy-Delay Product. Dynamic Voltage and Frequency Scaling (DVFS) design has acquired recent interest to increase energy efficiency during runtime. During periods of low utilization, a chip’s performance and power consumption can be adjusted by slowing down the c...Show More

Time-Borrowing Flip-Flop Architecture for Multi-Stage Timing Error Resilience in DVFS Processors

Avisekh Ghosh;Mohd Saif Naseem;Chaudhry Indra Kumar

Year: 2021 | Conference Paper |

A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design

Chaudhry Indra Kumar;Bulusu Anand

IEEE Transactions on Device and Materials Reliability
Year: 2020 | Volume: 20, Issue: 1 | Journal Article |
Cited by: Papers (27)
In this paper, a novel energy efficient 12T memory cell is proposed which is radiation hardened by design (RHD) to tolerate single-event multiple-node upsets (SEMNU) in near threshold voltage regime. The radiation hardness of the proposed memory cell is improved by controlling the cross coupled inverters' PMOS devices through dummy access transistors. We validated the proposed memory cell in STMic...Show More

A Highly Reliable and Energy Efficient Radiation Hardened 12T SRAM Cell Design

Chaudhry Indra Kumar;Bulusu Anand

Year: 2020 | Volume: 20, Issue: 1 | Journal Article |

A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design

Chaudhry Indra Kumar;Bulusu Anand

IEEE Transactions on Nuclear Science
Year: 2019 | Volume: 66, Issue: 10 | Journal Article |
Cited by: Papers (44)
This article presents an energy-efficient triple-node-upset (TNU)-tolerant latch in a subthreshold/near-threshold regime. The proposed latch provides the TNU tolerance using two restorer circuits (RCs) to hold the correct state and a three-input clocked combinational majority circuit (CMC). The RC is based on pull-up and pull-down paths, controlled by different susceptible nodes, results in better...Show More

A Highly Reliable and Energy-Efficient Triple-Node-Upset-Tolerant Latch Design

Chaudhry Indra Kumar;Bulusu Anand

Year: 2019 | Volume: 66, Issue: 10 | Journal Article |

A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches

Chaudhry Indra Kumar;Ishant Bhatia;Arvind Kumar Sharma;Deep Sehgal;H. S. Jatana;Anand Bulusu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year: 2019 | Volume: 27, Issue: 9 | Journal Article |
Cited by: Papers (2)
Near-threshold voltage (NTV) digital VLSI circuits, though important, have their sequential elements vulnerable to soft errors. The critical charge for a single event upset for a D-latch depends on its fan-out load, supply voltage, and transistor level parameters. A SPICE simulation-based estimation of the critical charge is highly resource/time intensive. In this paper, we propose a physics-based...Show More

A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches

Chaudhry Indra Kumar;Ishant Bhatia;Arvind Kumar Sharma;Deep Sehgal;H. S. Jatana;Anand Bulusu

Year: 2019 | Volume: 27, Issue: 9 | Journal Article |

Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability

Chaudhry Indra Kumar;Anand Bulusu

2018 14th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Year: 2018 | Conference Paper |
In modern CMOS technologies, meta-stability is becoming an important issue for designing sequential systems, especially in the near/sub-threshold regime. This is because, with a reduction in supply voltage, mean time between failures (MTBF) increases exponentially. This paper presents a detailed analysis of the meta-stability in design of near/sub-threshold resilient flip-flops. We show that a pro...Show More

Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability

Chaudhry Indra Kumar;Anand Bulusu

Year: 2018 | Conference Paper |

A novel energy-efficient self-correcting methodology employing INWE

Chaudhry Indra Kumar;Arvind Sharma;Sandeep Miryala;Anand Bulusu

2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
Year: 2016 | Conference Paper |
Operating VLSI circuits at near/sub-threshold region is emerging as the most important technique for low power applications. However, due to the increasing variability in sub-threshold regime, system performance and yield is at stake. Therefore, improved circuit techniques are needed with low power overhead which can essentially improve the yield. This paper presents a timing error Self Correcting...Show More

A novel energy-efficient self-correcting methodology employing INWE

Chaudhry Indra Kumar;Arvind Sharma;Sandeep Miryala;Anand Bulusu

Year: 2016 | Conference Paper |

A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique

Manisha Pattanaik;Shashank Parashar;Chaudhry Indra Kumar;Akanksha Chouhan;Vikas Mahor

2011 International Symposium on Electronic System Design
Year: 2011 | Conference Paper |
Cited by: Papers (1)
In this paper a new design technique is proposed using FTL (Feed through Logic) concept for high performance dynamic CMOS logic with high noise immunity and low power. FTL improves the performance of arithmetic circuits with a very long logic depth. In spite of its performance advantage, FTL suffers from reduced noise margin, direct path current and non-zero nominal low output voltage. The propose...Show More

A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique

Manisha Pattanaik;Shashank Parashar;Chaudhry Indra Kumar;Akanksha Chouhan;Vikas Mahor

Year: 2011 | Conference Paper |

An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance

Shashank Parashar;Chaudhry Indra Kumar;Manisha Pattanaik

2011 IEEE Computer Society Annual Symposium on VLSI
Year: 2011 | Conference Paper |
Cited by: Papers (1)
FTL improves the performance of arithmetic circuits, with a very long logic depth, while reducing the power dissipation, when compared with standard CMOS circuits. The feed through logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. As the supply voltage is scaling down, the circuit...Show More

An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance

Shashank Parashar;Chaudhry Indra Kumar;Manisha Pattanaik

Year: 2011 | Conference Paper |

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