A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs

Increasing a PLL’s reference frequency offers significant performance advantages, but doing so by increasing the PLL’s crystal oscillator frequency is not a viable option in many applications. Instead, a frequency doubler can be used to derive a reference signal with twice the frequency of the crystal oscillator, but conventional PLLs are highly sensitive to the crystal oscillator’s duty cycle error in such cases. Prior solutions to this problem involve calibration techniques which impose convergence speed versus accuracy tradeoffs. In contrast, this paper proposes a system modification which makes a PLL immune to such duty cycle errors without the need for calibration. The technique is presented and analyzed in the context of a delta-sigma frequency-to-digital converter ( $\Delta \Sigma $ -FDC) based PLL. Analysis and behavioral simulations with nonideal circuit parameters show that the worst-case convergence time is at least 10 times faster than that of the prior techniques. Additionally, the proposed $\Delta \Sigma $ -FDC includes other modifications which improve its performance relative to comparable prior $\Delta \Sigma $ -FDCs.

I. Introduction

Phase locked loops (PLLs) are critical components in communication systems, and their performance requirements continue to increase as communication system standards evolve. In particular, the demand for PLLs with sub-100-fs rms jitter is increasing to enable higher data rates in wireless and wireline communication systems [1], [2], [3], [4], [5], [6]. Furthermore, reciprocal-mixing requirements in some wireless applications require PLLs with reference spurs below –80 dBc.