A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector

Ring-oscillator (RO)-based phase-locked loops (PLLs) are very attractive for system-on-chip applications for their compactness and tuning range, but suffer from high jitter and supply noise sensitivity. This paper presents a sub-sampling phase detector (SSPD)-based feedforward noise cancellation (FFNC) technique to improve these drawbacks of the RO PLL. The FFNC scheme utilizes the already available SSPD output to perform cancellation with high sensitivity while utilizing low power and area overhead. The 2- to 2.8-GHz RO PLL proof-of-principle prototype occupies 0.022 mm
²
active area in 65 nm CMOS; it achieves a 633 fs rms jitter at 2.36 GHz with 5.86 mW power consumption and an figure of merit (FOM
_jitter
) of -236.3 dB. The cancellation reduces the jitter by 1.4×, the phase noise by 10.2 dB to -123.5 dBc/Hz at 300-kHz offset, and the RO supply sensitivity by 19.5 dB for a 1 mVpp 100-kHz noise tone on the RO supply.