Abstract:
As conventional CMOS scaling approaches its limits, the potential to sustain Moore's Law is being explored through 3D integration. The significant density limitations of ...Show MoreMetadata
Abstract:
As conventional CMOS scaling approaches its limits, the potential to sustain Moore's Law is being explored through 3D integration. The significant density limitations of commonly used TSV-based 3D stacked IC technologies are addressed by 3D monolithic solutions. However, this approach necessitates the reevaluation of optimal buffer insertion due to the utilization of heterogeneous technologies in different tiers and the significant alteration of wire characteristics resulting from wafer-to-wafer bonding processing constraints. In this paper, an optimization framework for monolithic 3D integration is introduced, specifically targeting the calculation of the optimal number of buffers, segments, and tiers to enhance data transmission performance in Network-on-Chip (NoC) links.
Published in: 2024 13th International Conference on Modern Circuits and Systems Technologies (MOCAST)
Date of Conference: 26-28 June 2024
Date Added to IEEE Xplore: 06 August 2024
ISBN Information:
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- IEEE Keywords
- Index Terms
- Heterogeneous 3D ,
- Monolithic 3D ,
- Optimization Framework ,
- Moore’s Law ,
- 3D Integration ,
- Energy Consumption ,
- Maximum And Minimum ,
- Linear Interpolation ,
- Segment Length ,
- Linker Length ,
- 3D Technology ,
- Optimization Goal ,
- Capacitive Coupling ,
- Maximum Delay ,
- Top-tier ,
- Technological Parameters ,
- Minimum Delay ,
- Interpolation Function ,
- Transmission Speed ,
- Total Capacitance ,
- Delay Distribution ,
- Metal Lines ,
- Global Interconnectedness ,
- Back-end-of-line ,
- Wire Resistance ,
- Transmission Line ,
- Tungsten ,
- Active Devices ,
- Impedance ,
- Parasite
- Author Keywords
Keywords assist with retrieval of results and provide a means to discovering other relevant content. Learn more.
- IEEE Keywords
- Index Terms
- Heterogeneous 3D ,
- Monolithic 3D ,
- Optimization Framework ,
- Moore’s Law ,
- 3D Integration ,
- Energy Consumption ,
- Maximum And Minimum ,
- Linear Interpolation ,
- Segment Length ,
- Linker Length ,
- 3D Technology ,
- Optimization Goal ,
- Capacitive Coupling ,
- Maximum Delay ,
- Top-tier ,
- Technological Parameters ,
- Minimum Delay ,
- Interpolation Function ,
- Transmission Speed ,
- Total Capacitance ,
- Delay Distribution ,
- Metal Lines ,
- Global Interconnectedness ,
- Back-end-of-line ,
- Wire Resistance ,
- Transmission Line ,
- Tungsten ,
- Active Devices ,
- Impedance ,
- Parasite
- Author Keywords