Analysis and Optimization of Delay-Power for Links in Heterogeneous Monolithic 3D NoCs

As conventional CMOS scaling approaches its limits, the potential to sustain Moore's Law is being explored through 3D integration. The significant density limitations of commonly used TSV-based 3D stacked IC technologies are addressed by 3D monolithic solutions. However, this approach necessitates the reevaluation of optimal buffer insertion due to the utilization of heterogeneous technologies in different tiers and the significant alteration of wire characteristics resulting from wafer-to-wafer bonding processing constraints. In this paper, an optimization framework for monolithic 3D integration is introduced, specifically targeting the calculation of the optimal number of buffers, segments, and tiers to enhance data transmission performance in Network-on-Chip (NoC) links.