Abstract:
The utilization of large datasets in applications results in significant energy expenditures attributed to frequent data shifts between memory and processing units. In-Me...Show MoreMetadata
Abstract:
The utilization of large datasets in applications results in significant energy expenditures attributed to frequent data shifts between memory and processing units. In-Memory-Computing (IMC) distinguishes itself by employing computations within a memory crossbar to perform logic operations, leading to enhanced computational speed and energy efficiency. This study introduces RASA-based subtractor, strategically improved for computation, and energy consumption. Subsequently, the proposed subtractor are employed to construct a comparator and facilitate pooling operations. The comparator is developed using the proposed subtractor, achieves the comparison in n steps for a n-bit comparator. Additionally, a n-bit min pooling operation for a \mathrm{n}\times \mathrm{n}\ (4\times 4) feature map requires 2^{n}-1 (15) steps. Energy consumption of the RASA design demonstrates hopped-up performance, showcasing an average savings of 87.42% and 89.98% compared to the ASA and Muller C based subtractor.
Date of Conference: 25-27 March 2024
Date Added to IEEE Xplore: 10 June 2024
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Indian Institute of Information Technology, Design and Manufacturing, (IIITDM), Kancheepuram
Indian Institute of Information Technology, Design and Manufacturing, (IIITDM), Kancheepuram
Indian Institute of Technology, Jodhpur
Indian Institute of Information Technology, Design and Manufacturing, (IIITDM), Kancheepuram
Indian Institute of Information Technology, Design and Manufacturing, (IIITDM), Kancheepuram
Indian Institute of Technology, Jodhpur