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Alireza Heidari - IEEE Xplore Author Profile

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Author details

Alireza Heidari

Also published under: Ali Reza Heidari

Publications

23

Citations

545

Publications by Year

20132024

Co-Authors:

Pablo AcunaVassilios G. AgelidisJamshid AghaeiAbdollah AhmadiEhsan Bagheri

Show All Co-Authors (44)

Alireza Heidari

Also published under: Ali Reza Heidari

Affiliation

Australian Energy Market Operator, Sydney, Australia

Publication Topics

Operational Costs,
Distribution Network,
Distribution System,
Mixed-integer Nonlinear Programming,
Normal Distribution,
Objective Function,
Power Generation,
Allowable Range,
Demand Side,
Market Power,
Microgrid,
Mixed Integer Linear Programming

Biography

Alireza Heidari (S’12–M’16) received the M.Sc. degree in power engineering from the Iran University of Science and Technology, Tehran, Iran, in 2006. He is currently working toward the Ph.D. degree in power engineering at the University of New South Wales, Sydney, Australia.,From 2006 to 2012, he was with the Faculty of Engineering, University of Zabol, Zabol, Iran. His research interests include power system operation, power system security and reliability, renewable energy resource integration, and application of optimization in power systems.(Based on document published on 1 March 2016).

Publications

23

Citations

545

Publications by Year

20132024

Co-Authors:

Pablo Acuna
Vassilios G. Agelidis
Jamshid Aghaei
Abdollah Ahmadi
Ehsan Bagheri

Show All Co-Authors (44)

Author's Published Works

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Showing 1-6 of 6 results

Journals (5)

Conferences (1)

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Subin Lee(6)
Jae-Hoon Han(5)
Jin Dong Song(4)
Dae-Myeong Geum(4)
Sang-Hyeon Kim(4)
Center for Opto-Electronic Materials and Devices, Korea Institute of Science and Technology, Seoul, South Korea(4)
Division of Nano and Information Technology, KIST School, Korea University of Science and Technology, Seoul, South Korea(1)
Department of Electrical and Computer Engineering, Korea University, Seoul, South Korea(1)
Center for Spintronics, KIST, Seoul, South Korea(1)
Korea Institute of Science and Technology (KIST), Seoul, South Korea(1)
IEEE Journal of the Electron Devices Society(3)
IEEE Electron Device Letters(2)
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)(1)
IEEE(6)
Burlingame, CA, USA(1)
Thermal Resistance(3)
3D Integration(2)
Contact Resistance(2)
Contact Structure(2)
Device Operation(2)

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Monolithic 3D Integration of InGaAs Photodetectors on Si MOSFETs Using Sequential Fabrication Process

Dae-Myeong Geum;Seong Kwang Kim;Subin Lee;Donghwan Lim;Hyung-Jun Kim;Chang Hwan Choi;Sang-Hyeon Kim

IEEE Electron Device Letters

Year: 2020 | Volume: 41, Issue: 3 | Journal Article |

Cited by: Papers (21)

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We demonstrated the monolithic 3D (M3D) integration of InGaAs photodetectors (PDs) on silicon-on-insulator metal-oxide-semiconductor field-effect transistors (SOI-MOSFETs) by the sequential process of InGaAs PDs on pre-fabricated SOI-MOSFETs. InGaAs PDs and SOI MOSFETs showed their original performances after integration and sequential process thanks to the low-temperature process. In addition, th...Show More

Monolithic 3D Integration of InGaAs Photodetectors on Si MOSFETs Using Sequential Fabrication Process

Dae-Myeong Geum;Seong Kwang Kim;Subin Lee;Donghwan Lim;Hyung-Jun Kim;Chang Hwan Choi;Sang-Hyeon Kim

IEEE Electron Device Letters

Year: 2020 | Volume: 41, Issue: 3 | Journal Article |

Epitaxial Lift-Off Technology for Large Size III–V-on-Insulator Substrate

Subin Lee;Seong Kwang Kim;Jae-Hoon Han;Jin Dong Song;Dong-Hwan Jun;Sang-Hyeon Kim

IEEE Electron Device Letters

Year: 2019 | Volume: 40, Issue: 11 | Journal Article |

Cited by: Papers (9)

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III-V materials can be a very good channel candidate for monolithic 3D (M3D) integration due to the potential of high-performance and lower process temperature as compared with Si, since a low process temperature is crucial to avoid degradation of bottom devices. For III-V M3D integration, material transfer techniques are important, and such processes should be enabled by low process costs on a la...Show More

Epitaxial Lift-Off Technology for Large Size III–V-on-Insulator Substrate

Subin Lee;Seong Kwang Kim;Jae-Hoon Han;Jin Dong Song;Dong-Hwan Jun;Sang-Hyeon Kim

IEEE Electron Device Letters

Year: 2019 | Volume: 40, Issue: 11 | Journal Article |

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

Sanghyeon Kim;Seong Kwang Kim;Sanghoon Shin;Jae-Hoon Han;Dae-Myeong Geum;Jae-Phil Shim;Subin Lee;Hansung Kim;Gunwu Ju;Jin Dong Song;M. A. Alam;Hyung-Jun Kim

IEEE Journal of the Electron Devices Society

Year: 2019 | Volume: 7 | Journal Article |

Cited by: Papers (22)

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Self-heating has emerged as an important performance/reliability challenge for modern MOSFETs. The challenge is further acerbated for III-V transistors, especially when integrated monolithically in a 3-D platform for applications in ultrafast logic, imagers, etc. A key challenge is the difficulty of heat-dissipation through the ultra-thin channels needed to ensure electrostatic integrity of scaled...Show More

Highly Stable Self-Aligned Ni-InGaAs and Non-Self-Aligned Mo Contact for Monolithic 3-D Integration of InGaAs MOSFETs

Sanghyeon Kim;Seong Kwang Kim;Sanghoon Shin;Jae-Hoon Han;Dae-Myeong Geum;Jae-Phil Shim;Subin Lee;Hansung Kim;Gunwu Ju;Jin Dong Song;M. A. Alam;Hyung-Jun Kim

IEEE Journal of the Electron Devices Society

Year: 2019 | Volume: 7 | Journal Article |

Heat Shunting by Innovative Source/Drain Contact to Enable Monolithic 3D Integration of InGaAs MOSFETs

SangHyeon Kim;Seong Kwang Kim;SangHoon Shin;Jae-Hoon Han;Dae-Myeong Geum;Jae-Phil Shim;Subin Lee;Han Sung Kim;Gunwu Ju;Jin Dong Song;Muhammad A. Alam;Hyung-jun Kim

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Year: 2018 | Conference Paper |

Cited by: Papers (2)

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Monolithic 3D (M3D) integration with III-V compound semiconductor (e.g., InGaAs) offers many advantages of reduced power consumption, footprint and enhanced performance and various functionality such as RF, imager, and Micro LED [1] [2] [3]. These advantages of M3D are often counterbalanced by persistent challenge of self-heating during device operation. A M3D system stacks multiple ultra-thin cha...Show More

Heat Shunting by Innovative Source/Drain Contact to Enable Monolithic 3D Integration of InGaAs MOSFETs

SangHyeon Kim;Seong Kwang Kim;SangHoon Shin;Jae-Hoon Han;Dae-Myeong Geum;Jae-Phil Shim;Subin Lee;Han Sung Kim;Gunwu Ju;Jin Dong Song;Muhammad A. Alam;Hyung-jun Kim

2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

Year: 2018 | Conference Paper |

Simulation Study on the Design of Sub- $kT/q$ Non-Hysteretic Negative Capacitance FET Using Capacitance Matching

Pavlo Bidenko;Subin Lee;Jae-Hoon Han;Jin Dong Song;Sang-Hyeon Kim

IEEE Journal of the Electron Devices Society

Year: 2018 | Volume: 6 | Journal Article |

Cited by: Papers (23)

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In this paper, approaches to obtain the sub-kT/q non-hysteretic operation mode in negative capacitance (NC) field-effect-transistors for a wide band of applied gate voltages, using capacitance matching, were systematically investigated using TCAD simulation. Unlike certain previous studies, in which the desired operation conditions were received for specific structures and materials, this study pr...Show More

Simulation Study on the Design of Sub- $kT/q$ Non-Hysteretic Negative Capacitance FET Using Capacitance Matching

Pavlo Bidenko;Subin Lee;Jae-Hoon Han;Jin Dong Song;Sang-Hyeon Kim

IEEE Journal of the Electron Devices Society

Year: 2018 | Volume: 6 | Journal Article |

Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III–V and Ge Materials

Sang-Hyeon Kim;Seong-Kwang Kim;Jae-Phil Shim;Dae-Myeong Geum;Gunwu Ju;Han-Sung Kim;Hee-Jeong Lim;Hyeong-Rak Lim;Jae-Hoon Han;Subin Lee;Ho-Sung Kim;Pavlo Bidenko;Chang-Mo Kang;Dong-Seon Lee;Jin-Dong Song;Won Jun Choi;Hyung-Jun Kim

IEEE Journal of the Electron Devices Society

Year: 2018 | Volume: 6 | Journal Article |

Cited by: Papers (27)

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Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devices. To solve this problem, we developed a low temperature III–V and Ge layer stacking process using ...Show More

Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III–V and Ge Materials

Sang-Hyeon Kim;Seong-Kwang Kim;Jae-Phil Shim;Dae-Myeong Geum;Gunwu Ju;Han-Sung Kim;Hee-Jeong Lim;Hyeong-Rak Lim;Jae-Hoon Han;Subin Lee;Ho-Sung Kim;Pavlo Bidenko;Chang-Mo Kang;Dong-Seon Lee;Jin-Dong Song;Won Jun Choi;Hyung-Jun Kim

IEEE Journal of the Electron Devices Society

Year: 2018 | Volume: 6 | Journal Article |

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