Abstract:
Moore's Law represents the cumulative effort by many participants to advance the productivity of electronic systems over the last 40+ years, resulting in enormous strides...Show MoreMetadata
Abstract:
Moore's Law represents the cumulative effort by many participants to advance the productivity of electronic systems over the last 40+ years, resulting in enormous strides in the capability and ubiquity of electronics. This paper identifies the innovation challenges the semiconductor industry must overcome in order to propel the advance of semiconductor technology to the cadence of Moore's Law. Key examples will highlight the solutions needed to enable advanced transistor and nano-scale interconnect fabrication. Solutions for tomorrow's low voltage, low power process technologies will introduce new materials, unprecedented levels of interface control and new energy sources while at the same time addressing the increasing cost and complexity needed to sustain Moore's Law well into the future.
Published in: IEEE Journal of the Electron Devices Society ( Volume: 1, Issue: 3, March 2013)
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Cymer, Inc., San Diego, CA, USA
Klaus Schuegraf is the Group Vice President for EUV Development & Engineering with Cymer Technologies, San Diego, CA, USA, an ASML company. In this role, he is responsible for leading Cymer's EUV source development activities, which herald the next generation of semiconductor lithography systems. He has broad experience in semiconductor technology and product development in dynamic random access memory (DRAM), static rand...Show More
Klaus Schuegraf is the Group Vice President for EUV Development & Engineering with Cymer Technologies, San Diego, CA, USA, an ASML company. In this role, he is responsible for leading Cymer's EUV source development activities, which herald the next generation of semiconductor lithography systems. He has broad experience in semiconductor technology and product development in dynamic random access memory (DRAM), static rand...View more
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Applied Materials, Santa Clara, CA, USA
Mathew C. Abraham received a B.S. degree from Haverford College, Haverford, PA, and M.S. and Ph.D. from Harvard University, Cambridge, MA in 1997, 2000 and 2004, respectively, all in physics.
From 2004 to 2008 he was an Engineer and Technology Manager at Intel Corporation working on various aspects of Yield, Process Development and Manufacturing of Flash memory products. In 2008, he joined Applied Materials Inc. working on...Show More
Mathew C. Abraham received a B.S. degree from Haverford College, Haverford, PA, and M.S. and Ph.D. from Harvard University, Cambridge, MA in 1997, 2000 and 2004, respectively, all in physics.
From 2004 to 2008 he was an Engineer and Technology Manager at Intel Corporation working on various aspects of Yield, Process Development and Manufacturing of Flash memory products. In 2008, he joined Applied Materials Inc. working on...View more

Applied Materials, Santa Clara, CA, USA
Adam Brand is the leader of the Transistor Technology group in Advanced Product Technology Development at Applied Materials Silicon Systems Group. He is working on understanding the logic process roadmap, and on solving the high value problems through Applied's equipment capability for CMOS channel, high-K/metal gate stack, contacting, and junction formation.
He joined Applied Materials in 2009, initially working as the Se...Show More
Adam Brand is the leader of the Transistor Technology group in Advanced Product Technology Development at Applied Materials Silicon Systems Group. He is working on understanding the logic process roadmap, and on solving the high value problems through Applied's equipment capability for CMOS channel, high-K/metal gate stack, contacting, and junction formation.
He joined Applied Materials in 2009, initially working as the Se...View more
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Applied Materials, Santa Clara, CA, USA
Mehul Naik is a Principal Member of the Technical Staff at Applied Materials, Santa Clara, CA, USA. Currently, he leads the Interconnect Program in the Advanced Product and Technology Development Team within the Silicon Systems Group. He has more than 15 years of experience in interconnect technology, and has co-authored over 40 conference and journal publications. He holds 30 U.S. patents covering metallization, low k, p...Show More
Mehul Naik is a Principal Member of the Technical Staff at Applied Materials, Santa Clara, CA, USA. Currently, he leads the Interconnect Program in the Advanced Product and Technology Development Team within the Silicon Systems Group. He has more than 15 years of experience in interconnect technology, and has co-authored over 40 conference and journal publications. He holds 30 U.S. patents covering metallization, low k, p...View more
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Applied Materials, Santa Clara, CA, USA
Randhir Thakur is the Executive Vice President and General Manager of the Silicon Systems Group (SSG) at Applied Materials, Inc., Santa Clara, CA, USA. He is focused on strengthening and extending the company's leadership in its core wafer fabrication equipment markets through organic and inorganic growth, achieving outstanding financial results, and improving operational efficiency. Under his direction, SSG has gained mo...Show More
Randhir Thakur is the Executive Vice President and General Manager of the Silicon Systems Group (SSG) at Applied Materials, Inc., Santa Clara, CA, USA. He is focused on strengthening and extending the company's leadership in its core wafer fabrication equipment markets through organic and inorganic growth, achieving outstanding financial results, and improving operational efficiency. Under his direction, SSG has gained mo...View more

Cymer, Inc., San Diego, CA, USA
Klaus Schuegraf is the Group Vice President for EUV Development & Engineering with Cymer Technologies, San Diego, CA, USA, an ASML company. In this role, he is responsible for leading Cymer's EUV source development activities, which herald the next generation of semiconductor lithography systems. He has broad experience in semiconductor technology and product development in dynamic random access memory (DRAM), static random access memory (SRAM), complementary metal oxide semiconductors (CMOS), non-volatile NAND flash memory, and semiconductor capital equipment.
Prior to Cymer, he was the Corporate Vice President and Chief Technology Officer (CTO) for the Silicon Systems Group (SSG) at Applied Materials, Inc., Santa Clara, CA, USA, where he was responsible for the company's technology leadership and innovation, aligning the company's technology roadmap with business objectives, increasing SSG's differentiated product portfolio and ensuring value to customers by leveraging understanding of technology inflections. Prior to Applied Materials, he was the Vice President of Technology at SanDisk Corporation, where he worked to define and execute the company's nonvolatile NAND flash and 3D memory road map and directed the implementation of a new 300 mm pilot line. Prior to SanDisk, he served as a Senior Director at Cypress Semiconductor Corporation, leading the company's SRAM foundry product development. Also at Cypress, Dr. Schuegraf led the development of six mixed-signal system-on-chip (SoC) microcontroller products. Prior to Cypress, he led CMOS and memory product development teams at Conexant Systems, Microchip Technology and Micron Technology.
He has guided technology program committees for the Institute of Electrical and Electronics Engineers (IEEE), including the Memory Technology Committee for the International Electron Devices Meeting (IEDM), the International Memory Workshop, and the International Reliability Physics Symposium and currently serves on the IEEE Electron Devices Society Semiconductor Manufacturing Committee.
Dr. Schuegraf received the Ph.D. degree in electrical engineering from the University of California, Berkeley, CA, USA, under the guidance of Professor Chenming Hu, world-renowned expert on semiconductor device reliability physics and non-volatile memories and a master of science degree in electrical engineering from Stanford University. He holds more than 85 patents and has authored more than 30 technical publications.
Klaus Schuegraf is the Group Vice President for EUV Development & Engineering with Cymer Technologies, San Diego, CA, USA, an ASML company. In this role, he is responsible for leading Cymer's EUV source development activities, which herald the next generation of semiconductor lithography systems. He has broad experience in semiconductor technology and product development in dynamic random access memory (DRAM), static random access memory (SRAM), complementary metal oxide semiconductors (CMOS), non-volatile NAND flash memory, and semiconductor capital equipment.
Prior to Cymer, he was the Corporate Vice President and Chief Technology Officer (CTO) for the Silicon Systems Group (SSG) at Applied Materials, Inc., Santa Clara, CA, USA, where he was responsible for the company's technology leadership and innovation, aligning the company's technology roadmap with business objectives, increasing SSG's differentiated product portfolio and ensuring value to customers by leveraging understanding of technology inflections. Prior to Applied Materials, he was the Vice President of Technology at SanDisk Corporation, where he worked to define and execute the company's nonvolatile NAND flash and 3D memory road map and directed the implementation of a new 300 mm pilot line. Prior to SanDisk, he served as a Senior Director at Cypress Semiconductor Corporation, leading the company's SRAM foundry product development. Also at Cypress, Dr. Schuegraf led the development of six mixed-signal system-on-chip (SoC) microcontroller products. Prior to Cypress, he led CMOS and memory product development teams at Conexant Systems, Microchip Technology and Micron Technology.
He has guided technology program committees for the Institute of Electrical and Electronics Engineers (IEEE), including the Memory Technology Committee for the International Electron Devices Meeting (IEDM), the International Memory Workshop, and the International Reliability Physics Symposium and currently serves on the IEEE Electron Devices Society Semiconductor Manufacturing Committee.
Dr. Schuegraf received the Ph.D. degree in electrical engineering from the University of California, Berkeley, CA, USA, under the guidance of Professor Chenming Hu, world-renowned expert on semiconductor device reliability physics and non-volatile memories and a master of science degree in electrical engineering from Stanford University. He holds more than 85 patents and has authored more than 30 technical publications.View more
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Applied Materials, Santa Clara, CA, USA
Mathew C. Abraham received a B.S. degree from Haverford College, Haverford, PA, and M.S. and Ph.D. from Harvard University, Cambridge, MA in 1997, 2000 and 2004, respectively, all in physics.
From 2004 to 2008 he was an Engineer and Technology Manager at Intel Corporation working on various aspects of Yield, Process Development and Manufacturing of Flash memory products. In 2008, he joined Applied Materials Inc. working on thin-film materials development and is at present Technology Director in the Silicon Systems Group. His research and technology development interests span electron transport and thin-film materials development for electrical, optical and magnetic devices.
Mathew C. Abraham received a B.S. degree from Haverford College, Haverford, PA, and M.S. and Ph.D. from Harvard University, Cambridge, MA in 1997, 2000 and 2004, respectively, all in physics.
From 2004 to 2008 he was an Engineer and Technology Manager at Intel Corporation working on various aspects of Yield, Process Development and Manufacturing of Flash memory products. In 2008, he joined Applied Materials Inc. working on thin-film materials development and is at present Technology Director in the Silicon Systems Group. His research and technology development interests span electron transport and thin-film materials development for electrical, optical and magnetic devices.View more

Applied Materials, Santa Clara, CA, USA
Adam Brand is the leader of the Transistor Technology group in Advanced Product Technology Development at Applied Materials Silicon Systems Group. He is working on understanding the logic process roadmap, and on solving the high value problems through Applied's equipment capability for CMOS channel, high-K/metal gate stack, contacting, and junction formation.
He joined Applied Materials in 2009, initially working as the Senior Director of Reliability and Interconnect/Packaging for the Sunfab thin film solar project. In 2008–2009, he was the Senior Director of the Periphery CMOS device group in Numonyx, focused on the 45 nm NOR flash technology. From 1991–2007 Adam worked in technology development at Intel on logic from 0.6 m to 90 nm and flash from 90 nm to 45 nm. He was the Manager of the transistor enhancement project for 180 nm and 130 nm logic, and delivered the 3.4 GHz Pentium4 process technology in 2003. He also led the 90 nm communications embedded logic device group and set the CMOS periphery architecture for the 45 nm SAC NOR flash.
Adam received the MSEE and BSEE degrees from from the Massachusetts Institute of Technology, Cambridge, MA, USA.
Adam Brand is the leader of the Transistor Technology group in Advanced Product Technology Development at Applied Materials Silicon Systems Group. He is working on understanding the logic process roadmap, and on solving the high value problems through Applied's equipment capability for CMOS channel, high-K/metal gate stack, contacting, and junction formation.
He joined Applied Materials in 2009, initially working as the Senior Director of Reliability and Interconnect/Packaging for the Sunfab thin film solar project. In 2008–2009, he was the Senior Director of the Periphery CMOS device group in Numonyx, focused on the 45 nm NOR flash technology. From 1991–2007 Adam worked in technology development at Intel on logic from 0.6 m to 90 nm and flash from 90 nm to 45 nm. He was the Manager of the transistor enhancement project for 180 nm and 130 nm logic, and delivered the 3.4 GHz Pentium4 process technology in 2003. He also led the 90 nm communications embedded logic device group and set the CMOS periphery architecture for the 45 nm SAC NOR flash.
Adam received the MSEE and BSEE degrees from from the Massachusetts Institute of Technology, Cambridge, MA, USA.View more

Applied Materials, Santa Clara, CA, USA
Mehul Naik is a Principal Member of the Technical Staff at Applied Materials, Santa Clara, CA, USA. Currently, he leads the Interconnect Program in the Advanced Product and Technology Development Team within the Silicon Systems Group. He has more than 15 years of experience in interconnect technology, and has co-authored over 40 conference and journal publications. He holds 30 U.S. patents covering metallization, low k, process integration, and patterning. He has co-chaired the Advanced Metallization Conference in 2008, and is currently on the executive committee for the Advanced Metallization Conference and the program committee for International Interconnect Technology Conference. He is a member of the Science Area Coordinating Committee for the Interconnect Packaging Science thrust in Semiconductor Research Corporation. Mehul received the Ph.D. degree in chemical engineering from the Rensselaer Polytechnic Institute, Troy, NY, USA.
Mehul Naik is a Principal Member of the Technical Staff at Applied Materials, Santa Clara, CA, USA. Currently, he leads the Interconnect Program in the Advanced Product and Technology Development Team within the Silicon Systems Group. He has more than 15 years of experience in interconnect technology, and has co-authored over 40 conference and journal publications. He holds 30 U.S. patents covering metallization, low k, process integration, and patterning. He has co-chaired the Advanced Metallization Conference in 2008, and is currently on the executive committee for the Advanced Metallization Conference and the program committee for International Interconnect Technology Conference. He is a member of the Science Area Coordinating Committee for the Interconnect Packaging Science thrust in Semiconductor Research Corporation. Mehul received the Ph.D. degree in chemical engineering from the Rensselaer Polytechnic Institute, Troy, NY, USA.View more

Applied Materials, Santa Clara, CA, USA
Randhir Thakur is the Executive Vice President and General Manager of the Silicon Systems Group (SSG) at Applied Materials, Inc., Santa Clara, CA, USA. He is focused on strengthening and extending the company's leadership in its core wafer fabrication equipment markets through organic and inorganic growth, achieving outstanding financial results, and improving operational efficiency. Under his direction, SSG has gained momentum in multiple business units and completed mergers with Semitool and Varian.
He rejoined the company in May 2008 as a Senior Vice President. He was previously the Executive Vice President of Technology, Fabs, Backend Manufacturing, and Worldwide Operations at SanDisk Corporation, Milpitas, CA, USA. He earlier held executive roles within various semiconductor product groups at Applied. Dr. Thakur serves on the Board of Directors for Marvell Semiconductor, Santa Clara, CA, USA. He holds more than 300 patents and in 2013 was named an IEEE Fellow for his ground-breaking leadership in development and implementation of single-wafer technology in semiconductor manufacturing. He received the Bachelor of Science degree with honors in electronics and telecommunications engineering from the Regional Engineering College, Kurukshetra, India, the Master of Science degree in electrical engineering from the University of Saskatchewan, Canada, and the Ph.D. in electrical engineering from the University of Oklahoma, Norman, OK, USA.
Randhir Thakur is the Executive Vice President and General Manager of the Silicon Systems Group (SSG) at Applied Materials, Inc., Santa Clara, CA, USA. He is focused on strengthening and extending the company's leadership in its core wafer fabrication equipment markets through organic and inorganic growth, achieving outstanding financial results, and improving operational efficiency. Under his direction, SSG has gained momentum in multiple business units and completed mergers with Semitool and Varian.
He rejoined the company in May 2008 as a Senior Vice President. He was previously the Executive Vice President of Technology, Fabs, Backend Manufacturing, and Worldwide Operations at SanDisk Corporation, Milpitas, CA, USA. He earlier held executive roles within various semiconductor product groups at Applied. Dr. Thakur serves on the Board of Directors for Marvell Semiconductor, Santa Clara, CA, USA. He holds more than 300 patents and in 2013 was named an IEEE Fellow for his ground-breaking leadership in development and implementation of single-wafer technology in semiconductor manufacturing. He received the Bachelor of Science degree with honors in electronics and telecommunications engineering from the Regional Engineering College, Kurukshetra, India, the Master of Science degree in electrical engineering from the University of Saskatchewan, Canada, and the Ph.D. in electrical engineering from the University of Oklahoma, Norman, OK, USA.View more