Universal Linear Optics Revisited: New Perspectives for Neuromorphic Computing With Silicon Photonics

Reprogrammable optical meshes comprise a subject of heightened interest for the execution of linear transformations, having a significant impact in numerous applications that extend from the implementation of optical switches up to neuromorphic computing. Herein, we review the state-of-the-art approaches for the realization of unitary transformations and universal linear operators in the photonic domain and present our recent work in the field, that allows for fidelity restorable and low-loss optical circuitry with single-step programmability. These advantages unlock a new framework for matrix-vector multiplications required by neuromorphic silicon photonic circuits, supporting: i) high-speed and high-accuracy neural network (NN) inference, ii) high-speed tiled matrix multiplication, iii) NN training and iv) programmable photonic NNs. This new potential is initially validated through recent experimental results using SiGe EAM technology and static weights and, subsequently, utilized for demonstrating experimentally the first Deep NN (DNN) where optical tiled matrix multiplication up to 50 GHz is realized, allowing optics to execute DNNs with large number of trainable parameters over a limited photonic hardware. Finally, the new performance framework is benchmarked against state-of-the-art NN processors and photonic NN roadmap projections, highlighting its perspectives to turn the energy and area efficiency promise of neuromorphic silicon photonics into a tangible reality.

I. Introduction

Recently, there has been a growing interest to perform fast and energy-efficient linear transformations between vectors or matrices, as they comprise a powerful tool for a wide range of applications in classical photonics, microwave communications, neuromorphic and quantum computing. In this context, researchers have steered their efforts into the development of highly parallelized hardware capable to undertake and accelerate these operations, with several graphic processing units (GPUs) [1], field programmable gate arrays [2] and application specific integrated circuits (ASICs) [3] having been demonstrated and fabricated within the last decade. Until now, the vast majority of the developed prototypes rely on electronic CMOS transistors that, due to their fundamental bandwidth and energy-efficiency limitations dictated by Moore's law [4], are approaching a computational plateau. On top of that, according to Amdahls’ law [5], the speed-up of parallel computation is saturated. To this end, linear optics have been brought again to the foreground aiming to catalyze and become the preferred computing hardware solution, since they offer THz bandwidth and ultra-low power consumption [6].