Novel Design partitioning technique for ASIC prototyping on multi-FPGA platforms using Graph Deep Learning

While prototyping ASIC designs on multi-FPGA platforms, challenges like partitioning, multiplexing limited I/O interconnections and mapping multiple clock-domains manually, cause significant delays and unpredictability in schedule. This process also requires highly skilled engineers who have deep understanding of the SoC designs. Automating this partitioning process of large designs onto multiple FPGAs using machine-learning techniques can potentially reduce time-to-market (TTM) in addition to potential savings in engineering resources. The problem requires clustering the various IPs in the design such that the number of signals between these clusters is a minimum, while ensuring the total resources of all IPs in a cluster does not go beyond the available limit in an actual FPGA. Once we get these clusters, we then need to map them to the exact FPGA on the multi-FPGA platform. We propose an algorithm modifying the GAP framework proposed in [4] that will automate the entire process of clustering and mapping, eliminating human intervention. We see good quality partitions with our experiments on 3 SoC designs and confirmed the feasibility of the generated partitions by manually mapping these onto the hardware and checking routing feasibility.