${O(N)}$O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform

A novel hardware architecture for Burrows-Wheeler Transform (BWT) scheme is presented. The core idea is to have a memory-free strategy that does not involve any software overhead during BWT operation. This is achieved by introducing a register-file concept and utilizing basic digital logic circuits to perform the entire BWT operation. Additionally, this is a kind of transformation scheme that does not utilize any kind of matrix during transformation, and thereby, it is free from run-time memory consumption. It efficiently handles the string terminating mechanism in the proposed design without involving any extra terminating symbol. This string terminator-free architecture eventually reduces additional operation and storage space to maintain the string, and thereby, the architecture does not necessitate any register read and write operations. This architecture exhibits efficient transformation without involving any indexing method or sorting mechanism during an inverse transformation operation. This architecture achieves $O(N)$ time complexity compared to $O(N^{2})$ and $O(N \log N)$ as experienced by the existing state-of-the-art approaches.

1 Introduction

The Burrows-Wheeler transform (BWT) [1] is an efficient data structure for reversible text transformation. The BWT and its alternative forms have been used in broad range of domains, such as data compression [2], [3], biological applications - next-generation sequencing [4], [5], [6], [7], [8], genomic data compression [9], [10], compression algorithms in communication systems [11], [12], text data search [13], compression of electrocardiogram (ECG) signals [14], [15], and image compression [16], [17].