Single-Event Upset Cross-Section Trends for D-FFs at the 5- and 7-nm Bulk FinFET Technology Nodes

At each advanced technology node, it is crucial to characterize and understand the mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm bulk FinFET node had resulted in a decrease in single-event upset (SEU) cross section at each node. However, this trend unexpectedly reversed for scaling from the 7-nm bulk FinFET node to the 5-nm bulk FinFET node. Experimental results show that the SEU cross sections for D flip-flops (D-FFs) designs at the 5-nm node are greater than those at the 7-nm for the whole range of particle linear energy transfer (LET) values tested. The 3-D technology computer-aided design (TCAD) and circuit-level simulations show that the increase in single-event (SE) cross Section with scaling to the 5-nm node is due to interactions between changes in drive current and nodal capacitances. The relative changes in these parameters increased SE transient (SET) pulsewidths and decreased feedback-loop delays, resulting in an increase in SE cross sections for the 5-nm node. In addition, the effects of threshold voltage and supply voltage on SEU cross section for both the 5- and 7-nm nodes are investigated. The SEU cross section for the D-FF designs at the 5-nm node shows a stronger dependence on both threshold voltage and supply voltage than that for the 7-nm node. As critical charge decreases with scaling, small differences in critical charge become more significant and manifest as large changes in SEU cross section, as observed for the 5-nm node. Designers will need to be particularly careful in assessing the overall SE susceptibility of systems developed using the 5-nm bulk FinFET node, particularly when different threshold voltage options and supply voltages are used across the IC.

I. Introduction

The pursuit for improved performance and power specifications drives the scaling of transistor sizes. Although these specifications will be enhanced with each new technology node, some reliability issues, such as single-event (SE) effects, may be unpredictable. The scaling of FinFETs results in a reduction of fin widths and an increase in fin heights, yielding decreased nodal capacitances and sensitive volumes for SE effects [1], [2]. The minimum amount of charge required for an upset () and the amount of charge collected () will both decrease as a result. Both of these factors are strong functions of fabrication process parameters, so the interplay between the factors will determine the overall SE response of designs implemented at a particular technology node [3], [4], [5].