Ultra-Low OSR Calibration Free MASH Noise Shaping SAR ADC

This paper demonstrates a proposed architecture of multi-stage noise-shaping (MASH) structure with noise shaping successive-approximation (NSSAR) ADC. The proposed intrinsic stable $4^{\mathrm{t}\mathrm{h}}$ order MASH NSSAR ADC can not only take advantage of sharp noise shaping effect but also gain benefits from hardware reuse. With ultra-low oversampling ratio (OSR) the MASH NSSAR is realized in Intel 22nm FinFET process with 0. 9V supply. The noise leakage introduced by the analog and digital filter mismatch will be analyzed and indicates no calibration needed in the proposed MASH under reasonable mismatch range. A PVT stable ring amplifier that can achieve high-speed settling is also proposed in this article. With 100MHz bandwidth (OSR=3) and 50MHz (OSR=6), the topology can achieve 78dB and 85dB SNDR respectively.

I. Introduction

The noise shaping successive-approximation (NSSAR) analog to digital converter (ADC) is a recently emerging hybrid ADC architecture that aims to combine the benefits of SAR algorithms and noise shaping effect [1–5]. However, due to the NSSAR ADC speed limitation and poor noise shaping effect, high bandwidth (BW) is quite hard to reach with good performance. In order to achieve higher BW, [1] takes advantage of process with oversampling ratio (OSR) equivalent to four can achieve 40MHzBW. However, the noise shaping effect is just first order which results in medium SNDR. Articles [2][4] both ultilize the order single loop structure, but the defective noise shaping influences the ADC performance. Also, since the order is implemented in a single loop, there is a potential stablility issue. Articles [3] and [5] incorporate time-interleaved (TI) in NSSAR ADC to reach high BW. However, channel mismatch shrinks the bandwidth and restricts the OSR. In this paper, a large BW NSSAR ADC with ultra-low OSR is proposed.