Abstract:
A 2/sup nd/ order multi-level /spl Sigma//spl Delta/ A/D converter for low-power multi-standard wireless receivers, in a single-poly 0.13 /spl mu/m digital CMOS process, ...Show MoreMetadata
Abstract:
A 2/sup nd/ order multi-level /spl Sigma//spl Delta/ A/D converter for low-power multi-standard wireless receivers, in a single-poly 0.13 /spl mu/m digital CMOS process, has 79/50 dB dynamic range for GSM/WCDMA. The 0.2 mm/sup 2/ chip consumes 2.4/2.9 mW at 1.5 V.
Published in: 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
Date of Conference: 07-07 February 2002
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7335-9
Contents 