A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC

This brief presents a single-loop third-order discrete-time delta-sigma ( $ {\Delta } {\Sigma }$ ) analog-to-digital converter (ADC). The proposed $ {\Delta } {\Sigma }$ ADC employs source-follower (SF)-based open-loop switched-capacitor (SC) integrators to achieve high-speed operation with efficient power consumption. A modified feed-forward topology is proposed to improve the linearity of the modulator using the SF-based integrators. An interpolating 4-bit flash quantizer with an embedded data weighted averaging (DWA) function is employed to address the nonlinearity of the feedback digital-to-analog converter (DAC) for high speed operation. The prototype ADC implemented in a 65nm CMOS technology achieves 75.4-dB dynamic range (DR) and 73.3-dB peak signal-to-noise-and-distortion ratio (SNDR) over 10-MHz bandwidth with an oversampling ratio (OSR) of 16. The power consumption of the modulator is 13.3-mW from a 1.1-V supply, resulting in the Walden and Schreier figure-of-merits (FoMW and FoMS) of 174-fJ/conversion-step and 164-dB, respectively.

I. Introduction

As wireless communication technology advances, the demand for analog-to-digital converters (ADCs) with wider bandwidth (BW) and higher dynamic range (DR) continues to grow. Advances of the scaled-down process technology increase the transit frequency of MOSFETs and thus broaden the bandwidth of delta-sigma () modulators, making them a good candidate for these applications. Discrete-time (DT) modulators based on switched-capacitor (SC) integrators have been widely used due to its robust operation with accurate loop filter transfer function against process, voltage, temperature (PVT) variations, low sensitivities to clock jitter and excess loop delay (ELD) [1]. However, the achievable bandwidth of the op-amp to satisfy the settling requirements, and rapid increase of power consumption along with the increased clock speed for wider signal bandwidth pose design challenges for DT modulators [2], [3].