A unified scheme for designing testable state machines

An approach for designing state machines that have built-in on-line and off-line testability is proposed. The next state logic is designed using transmission gates and tri-state buffers only. The resulting machines have scan-in/scan-out capability that allows off-line testing of the next state logic. The on-line testing capability for erroneous state transitions is achieved by EX-ORing the outputs of two registers that store the current and the next state of a machine, and checking for even parity at the outputs of the EX-OR gates.