Optimization of Wafer Dicing-Saw to Reduce the Chipping Defect by Using the Response Surface Methodology

With the development of IC integration scaling, chip after packaging is also sizing down. Dicing-Saw induces the high risk of wafer chipping by physical process characteristic especially when final thickness of chip is less than 100um. The process condition of Dicing-Saw is the key to control the physical damage during the Dicing-Saw process and maintain the high quality of chip. In this paper, we applied the Design of Experiment (DoE) to collect the result of process optimization and used Response Surface Methodology (RSM) to analyze the result to find out the best conditions to improve the yield loss by top-side chipping for the ultra-thin wafer sawing. Based on the result of DoE, matrix of feed speed and Z1 cutting height are the significant factors to reduce the risk of chipping and achieve high yield. The research contribute not only to knowing the best condition of wafer dicing saw process to reduce the wafer top-side chipping but also showing the DoE methodology performed well to improve the trouble solving efficiency.