Preliminary Results from a 49-Channel Neural Recording ASIC with Embedded Spike Compression in 28 nm CMOS

Neural interfaces allow better understanding of the brain by precisely measuring its activity, down to the level of single neurons. However, recording a high number of neurons requires a high number of analog-to-digital converters that generate a massive amount of data, making wireless transmission difficult. To solve this, we designed a neural recording application specific integrated circuit (ASIC) comprising a single ramp analog-to-digital converter (ADC) and a spike-by-spike digital compression circuit based on principal component analysis (PCA). The ASIC comprises 49 channels (each occupying an on-chip area of 50 × 60 µm²), a simulated noise of 12.3 µV RMS, and a power consumption of 4.6 µW. The circuit measures 1370 × 1370 µm² and consumes 828 µW. This paper presents the architecture and preliminary performance results of the neural recording ASIC and its compression circuit.