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A 4 × 4 Steerable 14-dBm EIRP Array on CMOS at 0.41 THz With a 2-D Distributed Oscillator Network | IEEE Journals & Magazine | IEEE Xplore

A 4 × 4 Steerable 14-dBm EIRP Array on CMOS at 0.41 THz With a 2-D Distributed Oscillator Network


Abstract:

Terahertz (THz) beamforming arrays are critical to address emerging applications in wireless communication, sensing, and imaging. Enabling such architectures, particularl...Show More

Abstract:

Terahertz (THz) beamforming arrays are critical to address emerging applications in wireless communication, sensing, and imaging. Enabling such architectures, particularly with respect to synchronization of distributed radiating THz sources, is very challenging due to the sensitivity of such synchronizations to variations of process, voltage, temperature (PVT), and device mismatches. In this article, we propose and demonstrate a multi-layer THz array architecture to address robust frequency synthesis, optimal harmonic THz power generation, and scalable phase generation for THz beamforming. The bottom-most layer of this multi-layer network consists of a scalable 2-D negative transconductance (−Gm) cells that collectively oscillates at the center frequency of 69.3 GHz, thereby establishing a robust frequency and phase distribution across the entire chip. By eliminating independent oscillation capability of each node and merging resonator and coupling structures into one single network, the 2-D mesh removes the possibility of moving out of synchronization due to PVT variations or device mismatches and forms the underlying frequency synthesis layer. Local frequency multiplication and radiating elements are placed across the 2-D THz array, and beamforming is enabled through varactor control in the -G_{m} cells. We demonstrate the proposed architecture in a 4\,\times \,4 array with effective isotropic radiation power (EIRP) of +14 dBm at 0.416 THz in a lensless setup using a 65-nm CMOS process with the beamforming capability of ±30° in both {E} - and {H} -planes.
Published in: IEEE Journal of Solid-State Circuits ( Volume: 57, Issue: 10, October 2022)
Page(s): 3125 - 3138
Date of Publication: 07 July 2022

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