TSV-less Power Delivery for Wafer-scale Assemblies and Interposers

Wafer-scale engines are gaining popularity amidst the rapidly rising demand for high-performance computing (HPC). Large interposers, such as Silicon Interconnect Fabric (Si-IF)[1], enable wafer-scale systems via dense integration of heterogeneous known-good-dielet (KGD) on a single silicon substrate. As a result, one can build an HPC processor as large as a 300 mm wafer. To deliver power and achieve external communication for such a large system, the conventional solution is to use through-silicon vias (TSVs) in the interposer substrate. In this work, we propose an alternative novel solution in which power and signals are routed around the die, in the inter-die gap, and then are routed on the substrate under the die and uniformly delivered to the dies. This solution has the following advantages: (1) TSV-less process which is inexpensive and reduces process complexity; (2) enablement of fine-pitch power/signal paths. This work focuses on power delivery of the novel structure, and a detailed simulation framework compares the power distribution network (PDN) electrical performance of the dielet-side method to the substrate-side method. We show that dielet sizes determine which PDN (TSV or dielet-side) should be used to reliably supply power to the assemblies. Based on our model, dielet-side power delivery is acceptable under conditions in which die sizes are smaller than 25 mm² and the power density is lower than 0.5 W/mm². A preliminary fabrication process was developed for power/ground paths of the dielet-side PDN in which through-polymer vias (TPVs) are employed. To demonstrate the compatibility of this novel integration methodology to thin (100 μm) dielet, a surrogate structure was designed and fabricated to mimic die-to-wafer assembly with 100 μm dielet. System encapsulation was achieved by thin Al2O3 deposition. Low-stress inter-die polymer isolation walls were built, and 500 μm width TPVs were fabricated by Cu electrochemical deposition.

I. Introduction

High-performance computing (HPC) systems are in widespread use. Transistor scaling has slowed down, therefore, systems and packages are growing in size to accommodate large amounts of computing, memory, and bandwidth. Wafer scale systems have the potential to provide the needed compute power at acceptable bisection bandwidths, power and latency[2]. These are of two types: one is to build a monolithic wafer-scale system, which is homogeneous and may suffer from yield issues. Another way is to utilize a wafer-scale platform on which a large number of known-good dielets (KGDs) are integrated with fine interconnect pitch. This way, SOC-like inter-die communication latency and bandwidth are achieved while heterogeneity is also fulfilled. However, for an interposer-based system, through-silicon vias (TSVs) are required both for power delivery and external connections.