Loading [a11y]/accessibility-menu.js
16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation | IEEE Conference Publication | IEEE Xplore

16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation


Abstract:

In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/...Show More

Abstract:

In nanometer MOSFETs, because of the small channel size, mesoscopic and even quantum effects can come into play. We have fabricated l6 nm NMOS devices featuring I/sub on/=400 /spl mu/A//spl mu/m and I/sub off/=0.8 /spl mu/A//spl mu/m and demonstrate that the FET principle is still confirmed at room temperature. We have deliberately used a non-overlapped SD/gate architecture, showing that, with adapted channel doping, it not only performs equally as well as the overlapped one, but also shows 1000/spl times/ reduced dispersion and is easily manufacturable. Finally, we show that quantization of energy in the channel motivates a study of performance at low temperature, and that the leading effect at low temperature and low voltage is Coulomb blockade.
Date of Conference: 02-05 December 2001
Date Added to IEEE Xplore: 07 August 2002
Print ISBN:0-7803-7050-3
Conference Location: Washington, DC, USA

Contact IEEE to Subscribe

References

References is not available for this document.