The Development of Accur ate Model Considering the Proximity Effect to Guide the BEOL Metal Scheme Design in the Advanced Logic Device

The accurate model to calculate nanoscale metal resistivity in the advanced logic device is developed. In this model, vicinity compensation for the proximity effect is considered together with bulk, grain boundary, and interface scatterings. With this model, the design optimization of Cu reflow and Ru liner thickness are studied in N10 and N5 technology nodes. Our modeling results agree with experimental insights of metal interconnects, guiding the design of future BEOL metal scheme and Power via applications.

I. Introduction

Power, performance, and density optimization has drived the continuous scaling of CMOS technology, where the routing interconnect of the densely-packed transistors in Back end of line (BEOL) poses the rapid increase of Cu line resistance. The scaling limitation of diffusion barrier, and the incorporation of Ru/Co liners for Cu fill and improvement of electro-migration integrity