Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods

As process technologies scale down, the accuracy requirements of parasitic capacitance extractions for integrated circuits significantly increase. This work introduces a novel accuracy-based hybrid parasitic capacitance extraction flow, where the chip is subdivided into windows, and each window’s capacitances are calculated using one of three extraction methods: field-solver, rule-based, and novel deep-neural-networks-based methods. This hybrid methodology uses a density-map feature representation as an input to neural-networks classifiers to determine an extraction method for each window. As an intermediate method between rule-based and field-solver methods, a novel deep-neural-networks-based extraction method is introduced. This intermediate level of accuracy and speed is needed since using only rule-based and field-solver methods results in using the field-solver most of the time for any required high accuracy extraction. This method uses a novel hybrid density-voltage representation as an input to improve its accuracy and speed. The proposed hybrid flow identifies the accuracy limits of the three extraction methods and directs each window to the fastest method that meets the user predetermined accuracy level. The proposed flow is tested on different real designs and showed outstanding accuracy and runtime as compared to commercial field-solver and rule-based tools. The results show that the proposed deep-neural-networks extraction method extracts capacitances of complicated structures with high accuracy (< 3% average error) and
$100\times $
faster than field-solvers. However, few outliers have an error exceeding 5% in extracted capacitances. Furthermore, the proposed hybrid flow managed to meet the required accuracy (< 5% error) with 99% accuracy and
$70\times $
faster than field-solvers.