A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations

Nonvolatile computing-in-memory (nvCIM) [1]–[4] is ideal for battery-powered tiny artificial intelligence (AI) edge devices that require nonvolatile data storage and low system-level power consumption. Data encryption/decryption (data-ED) is also required to prevent access to the neural network (NN) model weights and the personalized data used to improve inference accuracy. This paper presents an AI nvCIM data-ED-capable macro with high energy efficiency (EFMAC), a low macro-level read latency (tAC-M), a high read bandwidth (R-BW), and high-precision inputs (IN), weights (W), and outputs (OUT) for multiply-and-accumulate (MAC) operations. Prior nvCIM macros designed for MAC operations [1]–[3] do not support data-ED or a high number of accumulations (ACU). The use of a single NN layer also requires multiple cycles for full-channel MAC (MACFC-L operations. A low computing latency (tAC-FC-L) and high-precision nvCIM macro with data-ED design faces the following challenges: (1) long tAC-FC-L and low EFMAC for MACFC-L operations, which requires multiple memory accesses with a limited R-BW; (2) long tAC-M due to BL pre-charge (tPRE), signal development (tSD), sensing (tSA), and data-D (tOE); (3) High power consumption for BL precharge, particularly when using a high BL read voltage (VRD) to increase sensing yield.