AMD Core for Analog Signal Multiplication in 18nm FinFET Technology

This research presents an efficient method for performing analog multiplication. A system with dual voltage inputs and output as a voltage product is developed. Output voltage can be scaled by a factor, and the process has a very low latency. This study demonstrates that analog signal multiplication performed in the digital domain and then translated back to analog output signal can be accomplished with the least amount of delay. The goal of this project is to create a high-speed, low-power ADC, multiplier, and DAC for the AMD Core. Three blocks are used in the operation of an analog signal multiplier. Flash ADC design was chosen for its high performance. The multiplier's design is based on the Urdhva Tiryagbhyam Vedic Sutra, but it has been significantly optimized in terms of PPA using an inverted gate design. A high-speed 4-bit ADC with a power consumption of 1.2mW capable of 425 MSPS, a 10 GHz 4-bit multiplier with a power consumption of 50uW, and an 8-bit DAC with a period as short as 30ps and a power consumption of 21uW are all developed. The architecture of the analog signal multiplier allows for multiplication of two 425MHz signals with an average power consumption of 2.5mW at 0.8V. Cadence 18nm FinFET technology was used to de develop the proposed designs.