Optimisation Techniques for Multicore Architectures and Parallel Processing using OpenMP | IEEE Conference Publication | IEEE Xplore

Optimisation Techniques for Multicore Architectures and Parallel Processing using OpenMP


Abstract:

Multicore architecture amalgamates the logic of multiple processors into a single processor. Multicore architecture is widely used as it satiates needs such as higher per...Show More

Abstract:

Multicore architecture amalgamates the logic of multiple processors into a single processor. Multicore architecture is widely used as it satiates needs such as higher performance, energy-efficiency, and lower execution times by executing tasks contemporaneously. Parallelism is a crucial factor in acquiring high performance in multicore processors. Multicore architecture and parallel processing work in tandem with each other by partitioning tasks and executing them in parallel. This paper lays emphasis on cache coherence protocols that are used to resolve the cache coherence problem pervasively existent in shared memory multicore architecture. Cache coherence protocols are categorised into hardware-based protocols, software-based protocols and hybrid approach. The paper further bequeaths into global scheduling heuristics that is applied to multicore architectures to exploit fine grained parallelism. Manoeuvring fine grained parallelism to the compiler accrues better performance. In addition to that, SEU fault-injection on multicore processors is also incorporated into this report. Single Event Upset (SEU) is a phenomena prevalent in multicore architectures. The multiplicity of cores in multicore architectures makes it vulnerable to SEU's causing unforeseen soft errors. SEU fault-injection technique involves injecting faults into specific components. The performance of multicore architecture and parallel processing is also evaluated using OpenMP. OpenMP is an Application Programming Interface (API) that enables parallel execution on multicore processors. Some of the ways the performance of multicore architecture is increased is by means of employing cache coherence protocols, global scheduling techniques, applying OpenMP and through SEU fault-injections.
Date of Conference: 07-08 December 2021
Date Added to IEEE Xplore: 24 January 2022
ISBN Information:
Conference Location: Sakheer, Bahrain

References

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