High Reliability Solution of 2.5D Package Technologies

In recent years, high performance computing (HPC) and networking products have been integrating more functions into the larger die size with high density transistor. For High-end Router/ Switch product requirement, its wafer Si node development trend is from 28nm to 5nm but with low wafer yield and high wafer cost at large advanced Si node SoC die. Semiconductor industry also is facing the limit of Moore’s Law. The Heterogeneous/ homogeneous integration and chiplet idea come out and be popular in recently years due to separated small die can increase gross die and higher wafer yield for cost saving. Heterogeneous/ homogeneous integration package is a solution to support multiple die package requirements and get higher system performance in parallel with Moore’s Law. This Package is like 3D IC platform for heterogeneous/ homogeneous integration between two chips, it provides high computing speed and high bandwidth memory for massive data transmission. It is important for HPC product that networking server and AI training need lower latency. HPC package evaluation is a key item for foundry house and OSAT. 2.5D (Chip on Wafer on Substrate, CoWoS) package with a through silicon via (TSV) interposer already production in market. 2.5D advantages are finest L/S, more bump density, bandwidth density, and interposer provide better chip module warpage control, no CTE mismatch cause Underfill crack like FOMCM (Fan Out Muti-Chip Module) and more mature process for multiple dies integration solution. SPIL have develop 2.5D structure with molding chip module for years to provide high end product protection and reliability for advanced die function and whole package. Chip module warpage is a key and define by chips module layout design. If two small chips place different side of ASIC die, 2.5D package will have unbalance chip module stress condition due to larger mold area than 2 small chips place in same side of ASIC. There might be risk like C4 bump non-wetting or bridge bump, TSI crack and bad package coplanarity control. These issue need extra time for material and recipe fine-tune or need to change ASIC design. In this paper, we use filler die as solution for unbalance chip module 2.5D by increasing Si area in multichip module to keep original design for electric path. The simulation result shows more filler dies has better chip module warpage, low risk for package warpage and TSI stress because Si filler die help whole wafer warpage control in Mechanical properties result. In real sample result, 2.5D with filler dies structure shows all data in spec, better chip module warpage control and package coplanarity Cpk than no filler die device. Crosssection image of real structure show no not-wetting bump, bridge bump and TSI crack issue during process. This paper demonstrate 2.5D with filler die solution to be high reliability solution for heterogeneous/ homogeneous integration solution.