Abstract:
This paper presents a load-pull technique where a limited range of matching networks are synthesised on-chip to sample discrete points on the complex impedance plane. Cop...Show MoreMetadata
Abstract:
This paper presents a load-pull technique where a limited range of matching networks are synthesised on-chip to sample discrete points on the complex impedance plane. Copies of the matching networks are applied to the output of a selected transistor to enable power measurements. Data is combined together in a Focus load-pull file to allow the generation of load-pull contours. The novel technique does not use an external load-pull tuner; it utilises the excellent repeatability of multiple GaAs integrated circuit devices and an on-chip pi-attenuator for a reference load. Comparison to simulation results using a compact circuit model is promising at 94 GHz. The reflection coefficient magnitude error was less than 0.05, and the angle error was less than 1 degree with limited source power in the measurement.
Published in: 2021 IEEE Asia-Pacific Microwave Conference (APMC)
Date of Conference: 28 November 2021 - 01 December 2021
Date Added to IEEE Xplore: 03 January 2022
ISBN Information: