AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow

The security of system-on-chip (SoC) designs is threatened by many vulnerabilities introduced by untrusted third-party IPs, and designers and CAD tools' lack of awareness of security requirements. Ensuring the security of an SoC has become highly challenging due to the diverse threat models, high design complexity, and lack of effective security-aware verification solutions. Moreover, new security vulnerabilities are introduced during the design transformation from higher to lower abstraction levels. As a result, security verification becomes a major bottleneck that should be performed at every level of design abstraction. Reducing the verification effort by mapping the security properties at different design stages could be an efficient solution to lower the total verification time if the new vulnerabilities introduced at different abstraction levels are addressed properly. To address this challenge, we introduce AutoMap that, in addition to the mapping, extends and expands the security properties to identify new vulnerabilities introduced when the design moves from higher-to lower-level abstraction. Starting at the higher abstraction level with a defined set of security properties for the target threat models, AutoMap automatically maps the properties to the lower levels of abstraction to reduce the verification effort. Furthermore, it extends and expands the properties to cover new vulnerabilities introduced by design transformations and updates to the lower abstraction level. We demonstrate AutoMap's efficacy by applying it to AES, RSA, and SHA256 at C++, RTL, and gate-level. We show that AutoMap effectively facilitates the detection of security vulnerabilities from different sources during the design transformation.

I. Introduction

With the increasing complexity of modern system-on-chips (SoCs), accommodating various in-house and third-party intellectual properties (IPs), and including numerous security assets (keys, biometrics, personal info, etc.), performing rigorous security verification would be a daunting task while addressing a diverse set of threats [1]–[3]. This rising complexity leads to a significant increase in verification time, and effort [4] that exacerbates meeting the very tight time-to-market budget. During functional verification, this is often attempted to be tackled by reusing the verification effort in different abstraction levels of the design flow [5]. However, most of the techniques are limited only to two abstraction levels, namely Transaction Level Modeling (TLM) and Register Transfer Level (RTL) [6]–[10].