I. Introduction
With the increasing complexity of modern system-on-chips (SoCs), accommodating various in-house and third-party intellectual properties (IPs), and including numerous security assets (keys, biometrics, personal info, etc.), performing rigorous security verification would be a daunting task while addressing a diverse set of threats [1]–[3]. This rising complexity leads to a significant increase in verification time, and effort [4] that exacerbates meeting the very tight time-to-market budget. During functional verification, this is often attempted to be tackled by reusing the verification effort in different abstraction levels of the design flow [5]. However, most of the techniques are limited only to two abstraction levels, namely Transaction Level Modeling (TLM) and Register Transfer Level (RTL) [6]–[10].