Design and Analysis of First Order Sigma-Delta Modulator Based on Switched Capacitor Integrator (130nm)

The modern world is digitally advancing rapidly. However, the real world is analog which requires an adequate converter. The analysis of Such an Analog-to-digital modulator is designed and presented in this paper. The ΣΔ-modulator inherits an OTAas the main block. Where the modulator is a discrete-time switched capacitor integrator, Discrete-time low pass integrator and a double tail comparator as 1-bit ADC/quantizer obtain a first-order noise shaping modulator. The modulator implemented at 0.13um CMOS technology using 1.3v supply voltage. That obtained the SFDR of 72.58dB, THD of 0.489 and overall power dissipation (excluding D-flip flips) of the modulator is 1.147mw.

I. Introduction

Analog-to-digital (ADC) and digital-to-analog (DAC) converters play a vital role in converting an analog signal (Infinite valued over time) into a digital code (either a zero or VDD) and vice versa [1]. As the technology node keeps shrinking the design techniques are rapidly changing for every new technology that is emerging. The ADC designer needs a vast amount of knowledge on digital, analog, and mixed-signal IC design. However, the sigma-delta ADC is not the case, where the complex and accurate analog circuitry are not required to obtain high-resolution digital equivalent code [2]. The sigma-delta ADC is known for high resolution and low bandwidth ADC, which is possible by the technique over sampling rate (fs= (2^N) * Nyquist rate) i.e. N is a positive integer greater than one [3].