A 0. 94-\mu \mathrm{V}_{\text{rms}}$ Input Noise Pixel-Level Continuous Time $\Sigma\Delta$ IADC Interface for THz Sensing

The goal of this work is the design, realization, and characterization of a pixel-level front-end in $0.15\mu \mathrm{m}$ CMOS technology, that allows to directly convert in the digital domain the weak output signal from the Field-Effect Transistor (FET) TeraHertz (THz) detector, in a noise-efficient way. The chosen architecture is a Continuous-Time Sigma-Delta Incremental Analog-to-Digital Converter (CT $\Sigma\Delta$ IADC) with a current DAC feedback, chopper technique and digital lock-in modulation. The measured SNR of this interface is 67.45dB, corresponding to an equivalent number of bit (ENOB) of 10.91. The pixel readout area is 0.072mm², and the power consumption is $65\mu \mathrm{W}$ from 1.8V supply. The Noise Equivalent Power (NEP) of the THz detector and readout chain is $268\text{pW}/\sqrt{\text{Hz}}$. The readout channel Input Referred Noise (IRN) is $1.2\mu \text{Vrms}$ with the FET, and $0.94\mu \text{Vrms}$ for the channel without detector.