TCAD study of latch-up sensitivity to wafer thinning below 500 nm

The sensitivity of latch-up to wafer thickness is investigated with TCAD simulations. The dependency of bipolar and well resistances on substrate thickness is first evaluated, and later used to assess the loop gain of the latch-up circuit. Transient simulations are finally employed to assess the latch-up resilience as a function of substrate thickness.

I. Introduction

3D technology makes extensive use of wafer thinning tech-nology. Its adoption in memory [1] and logic products [2] raises the question of CMOS integrity in thin wafers. Previous reports have addressed issues such as mechanical stress and back-side contamination which may affect the front-end below ∼50 µm thickness [3], [4].