Abstract:
The sensitivity of latch-up to wafer thickness is investigated with TCAD simulations. The dependency of bipolar and well resistances on substrate thickness is first evalu...Show MoreMetadata
Abstract:
The sensitivity of latch-up to wafer thickness is investigated with TCAD simulations. The dependency of bipolar and well resistances on substrate thickness is first evaluated, and later used to assess the loop gain of the latch-up circuit. Transient simulations are finally employed to assess the latch-up resilience as a function of substrate thickness.
Published in: 2021 International Semiconductor Conference (CAS)
Date of Conference: 06-08 October 2021
Date Added to IEEE Xplore: 18 November 2021
ISBN Information: