An Incremental Placement Flow for Advanced FPGAs With Timing Awareness

As interconnects dominate circuit performance in modern field programmable gate arrays (FPGAs), placement becomes a crucial stage for timing closure. Traditional FPGA placers seldom consider the timing constraints and, thus, may lead to illegal routing solutions. In this article, we present an incremental timing-driven placement flow for advanced FPGAs. First, a timing-based global placement strategy is designed to guide heterogeneous blocks to desired locations with satisfied timing constraints. Then, a timing-aware packing algorithm is developed to mitigate the design complexity while improving the timing results. Finally, we propose a critical path-based optimization method to generate optimized layout without timing violations. We evaluate our algorithm based on industrial circuits using an advanced FPGA device. The experimental results show that our placer achieves a 5.1% improvement in worst slack and produce placements that require 16.7% less time to route when compared with the leading commercial tool Xilinx Vivado.

I. Introduction

Field-programmable arrays (FPGAs) are premanufactured integrated circuits designed to be configured for user customization [1]. With in-field reprogrammability and nonrecurring costs, FPGAs have emerged as a popular style in modern circuit designs [2]. Beyond the success in traditional fast application-specific integrated circuit (ASIC) prototyping, FPGAs also produce feasible solutions for modern applications, such as high-frequency trading, deep learning, and cryptocurrency mining [3].