Junctionless Nanowire Transistors Based Wilson Current Mirror Configuration

In this paper, a Wilson current mirror based on junctionless nanowire transistors (JNTs) is evaluated for the first time. Considering that the Wilson current mirror exhibits an enhanced output resistance with respect to the common source configuration, this study is focused on verifying the mirroring accuracy of different transistor dimensions. Also, the work examines the impact of the transistor feedback circuit on the output resistance and the current transfer ratio. The current mirror has been evaluated through numerical simulations, which were calibrated to experimental data of single devices.

I. Introduction

Considering the complex fabrication of small transistors with junctions and Short Channel Effects (SCEs) related to the drain control over the channel charges with the transistor reduction, the Junctionless Nanowire Transistor raised as a solution to minimize the drain and source effect over the channel with the reduction of the transistor dimensions [1]. Since the device presents a constant doping profile along all the silicon active layer, the device seems to have a better electrical characteristic with respect to the MOSFET with junctions, reflecting on a better subthreshold slope and a low drain induced barrier lowering (DIBL) [2].