Fault model minimum coverages of neighborhood pattern-sensitive faults for the March 12N implemented with/without address scrambling. Fault coverages of 80.21% (154) neig...
Abstract:
A memory fault model (FM) is an abstraction of the physical mechanism of memory failure. When the physical failure mechanisms are not fully represented in FMs, the covera...Show MoreMetadata
Abstract:
A memory fault model (FM) is an abstraction of the physical mechanism of memory failure. When the physical failure mechanisms are not fully represented in FMs, the coverage of the FMs can be different from that of the failure mechanisms. However, it is impractical (or impossible) to model every electrical aspect of the failure mechanisms with one or more FMs. This problem has become even worse with emerging technologies. Thus, in this study, the fault coverage (FC) consequences are investigated when the physical memory characteristics are not properly linked to the FMs or even test algorithms. Three physical characteristics were considered for this exploration: electrical masking, address scrambling, and electrical neighborhoods. To this end, memory fault simulations were performed, and the test algorithms were re-evaluated in terms of FC. Simulations were performed on the 1 kB area of the example SRAM model; three classes of FMs (56 static faults (SFs), 126 dynamic faults (DFs), and 192 neighborhood pattern-sensitive faults (NPSFs)) were simulated for FC evaluation; and March MSS, March MD2, and March 12N were used to re-evaluate the FCs of SFs, DFs, and NPSFs, respectively. From the simulation results, we observed the negative impact of physical characteristics on FC. When masking was considered, FC reductions of 10.72% SFs and 9.52% DFs were observed; when address scrambling was not available, an FC reduction of 80.21% NPSFs was observed. Finally, considering electrical neighborhood changes depending on the physical memory structure, an FC reduction of 41.67% NPSFs was observed.
Fault model minimum coverages of neighborhood pattern-sensitive faults for the March 12N implemented with/without address scrambling. Fault coverages of 80.21% (154) neig...
Published in: IEEE Access ( Volume: 9)
Funding Agency:
Department of Electronics Engineering, Hanyang University, Ansan, Republic of Korea
Kiseok Lee received the B.S. degree in electrical and communication engineering from Hanyang University, South Korea, in 2013, where he is currently pursuing the Ph.D. degree in electronics and communication engineering.
His research interests include memory test pattern optimization, memory fault modeling, and memory fault diagnosis. He is also conducting research related to random patterns to determine their benefits. Hi...Show More
Kiseok Lee received the B.S. degree in electrical and communication engineering from Hanyang University, South Korea, in 2013, where he is currently pursuing the Ph.D. degree in electronics and communication engineering.
His research interests include memory test pattern optimization, memory fault modeling, and memory fault diagnosis. He is also conducting research related to random patterns to determine their benefits. Hi...View more
Department of Electronics Engineering, Hanyang University, Ansan, Republic of Korea
Jeonghwan Kim received the B.S. degree in electronic engineering from Hoseo University, Asan, South Korea, in 2019. He is currently pursuing the Ph.D. degree in electronic engineering with Hanyang University.
His research interests include memory test methodologies, memory failure analysis at the system level, and memory fault diagnosis. He is also conducting research on memory reliability in a server-class system environm...Show More
Jeonghwan Kim received the B.S. degree in electronic engineering from Hoseo University, Asan, South Korea, in 2019. He is currently pursuing the Ph.D. degree in electronic engineering with Hanyang University.
His research interests include memory test methodologies, memory failure analysis at the system level, and memory fault diagnosis. He is also conducting research on memory reliability in a server-class system environm...View more
Department of Electronics Engineering, Hanyang University, Ansan, Republic of Korea
Sanghyeon Baeg (Member, IEEE) received the B.S. degree in electronic engineering from Hanyang University, Seoul, South Korea, in 1986, and the M.S. and Ph.D. degrees in electrical and computer engineering from The University of Texas at Austin, in 1988 and 1991, respectively. From 1994 to 1997, he was a Staff Researcher with Samsung Electronics Company Ltd., Kihung, South Korea. In 1995, he was dispatched to Samsung Semic...Show More
Sanghyeon Baeg (Member, IEEE) received the B.S. degree in electronic engineering from Hanyang University, Seoul, South Korea, in 1986, and the M.S. and Ph.D. degrees in electrical and computer engineering from The University of Texas at Austin, in 1988 and 1991, respectively. From 1994 to 1997, he was a Staff Researcher with Samsung Electronics Company Ltd., Kihung, South Korea. In 1995, he was dispatched to Samsung Semic...View more
Contents Department of Electronics Engineering, Hanyang University, Ansan, Republic of Korea
Kiseok Lee received the B.S. degree in electrical and communication engineering from Hanyang University, South Korea, in 2013, where he is currently pursuing the Ph.D. degree in electronics and communication engineering.
His research interests include memory test pattern optimization, memory fault modeling, and memory fault diagnosis. He is also conducting research related to random patterns to determine their benefits. His work also focuses on noise-inducing patterns in very large-scale integration (VLSI) circuits and systems with interconnect test patterns.
Kiseok Lee received the B.S. degree in electrical and communication engineering from Hanyang University, South Korea, in 2013, where he is currently pursuing the Ph.D. degree in electronics and communication engineering.
His research interests include memory test pattern optimization, memory fault modeling, and memory fault diagnosis. He is also conducting research related to random patterns to determine their benefits. His work also focuses on noise-inducing patterns in very large-scale integration (VLSI) circuits and systems with interconnect test patterns.View more
Department of Electronics Engineering, Hanyang University, Ansan, Republic of Korea
Jeonghwan Kim received the B.S. degree in electronic engineering from Hoseo University, Asan, South Korea, in 2019. He is currently pursuing the Ph.D. degree in electronic engineering with Hanyang University.
His research interests include memory test methodologies, memory failure analysis at the system level, and memory fault diagnosis. He is also conducting research on memory reliability in a server-class system environment.
Jeonghwan Kim received the B.S. degree in electronic engineering from Hoseo University, Asan, South Korea, in 2019. He is currently pursuing the Ph.D. degree in electronic engineering with Hanyang University.
His research interests include memory test methodologies, memory failure analysis at the system level, and memory fault diagnosis. He is also conducting research on memory reliability in a server-class system environment.View more
Department of Electronics Engineering, Hanyang University, Ansan, Republic of Korea
Sanghyeon Baeg (Member, IEEE) received the B.S. degree in electronic engineering from Hanyang University, Seoul, South Korea, in 1986, and the M.S. and Ph.D. degrees in electrical and computer engineering from The University of Texas at Austin, in 1988 and 1991, respectively. From 1994 to 1997, he was a Staff Researcher with Samsung Electronics Company Ltd., Kihung, South Korea. In 1995, he was dispatched to Samsung Semiconductor, Inc., San Jose, CA, USA, and worked as a member of the Technical Staff. In 1997, he joined Cisco Systems, Inc., San Jose, and worked as a Hardware Engineer, a Technical Leader, and a Hardware Manager. Since 2004, he has been working as a Professor with the School of Electronics and Communication Engineering, Hanyang University, Ansan, South Korea. His work has focused on reliable computing, soft errors, low-power content-addressable memory (CAM), and VLSI DFT implementation and methodologies. He is the holder of many U.S. patents in these fields. He was a recipient of the Inventor Recognition Award from Semiconductor Research Cooperation, in 1993. He was an IEEE 1149.6 Working Group Member, in 2003. He has been served as an Organizing Member for the Institute of Semiconductor Test of Korea, since 2012.
Sanghyeon Baeg (Member, IEEE) received the B.S. degree in electronic engineering from Hanyang University, Seoul, South Korea, in 1986, and the M.S. and Ph.D. degrees in electrical and computer engineering from The University of Texas at Austin, in 1988 and 1991, respectively. From 1994 to 1997, he was a Staff Researcher with Samsung Electronics Company Ltd., Kihung, South Korea. In 1995, he was dispatched to Samsung Semiconductor, Inc., San Jose, CA, USA, and worked as a member of the Technical Staff. In 1997, he joined Cisco Systems, Inc., San Jose, and worked as a Hardware Engineer, a Technical Leader, and a Hardware Manager. Since 2004, he has been working as a Professor with the School of Electronics and Communication Engineering, Hanyang University, Ansan, South Korea. His work has focused on reliable computing, soft errors, low-power content-addressable memory (CAM), and VLSI DFT implementation and methodologies. He is the holder of many U.S. patents in these fields. He was a recipient of the Inventor Recognition Award from Semiconductor Research Cooperation, in 1993. He was an IEEE 1149.6 Working Group Member, in 2003. He has been served as an Organizing Member for the Institute of Semiconductor Test of Korea, since 2012.View more